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Commit 68061b42 authored by Andrei Tosa's avatar Andrei Tosa
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Tested version for unsigned 32bit

parent 194b5258
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.gitignore
View file @ 68061b42
......@@ -10,3 +10,7 @@ emconfig.json
_x
.run
.Xil
.csv
.ipcache
.wcfg
.wdb
profile_kernels.csv 0 → 100644
View file @ 68061b42
Compute Units: Running Time and Stalls
Compute Unit, Running Time (us), Intra-Kernel Dataflow Stalls (%), External Memory Stalls (%), External Stream Stalls (%)
rndgen_1,0.570,0.000,12.865,0.000
Functions: Running Time and Stalls
Compute Unit, Function, Running Time (us), Intra-Kernel Dataflow Stalls (%), External Memory Stalls (%), External Stream Stalls (%)
Compute Units: Port Data Transfer
Compute Unit, Port, Write Time (us), Outstanding Write (%), Read Time (us), Outstanding Read (%)
rndgen_1,m_axi_gmem,0.183,32.164,0.000,0.000
src/defines.hpp 0 → 100644
View file @ 68061b42
#pragma once
#define REG_SIZE 32
#define SET_SIZE 100
#define F1(x, y, z) ((x) ^ ((y) | (z)))
#define F2(x, y, z) (!(x) ^ ((y) | (z)))
src/host.cpp
View file @ 68061b42
#include "host.hpp"
//#include "defines.hpp"
#include <iostream>
#include <fstream>
......@@ -10,18 +11,20 @@ int main(int argc, char** argv)
}
std::string binaryFile = argv[1];
size_t vector_size_bytes = sizeof(int) * DATA_SIZE;
size_t vector_size_bytes = sizeof(int) * SET_SIZE;
cl_int err;
unsigned fileBufSize;
// Allocate Memory in Host Memory
std::vector<int,aligned_allocator<int>> source_hw_results(DATA_SIZE);
std::vector<int,aligned_allocator<int>> source_sw_results(DATA_SIZE);
uint32_t seed = 1;
std::vector<uint32_t,aligned_allocator<uint32_t>> source_hw_results(SET_SIZE);
std::vector<uint32_t,aligned_allocator<uint32_t>> source_sw_results(SET_SIZE);
// Create the test data
for(int i = 0 ; i < DATA_SIZE ; i++){
for(int i = 0 ; i < SET_SIZE ; i++){
source_sw_results[i] = 0;
source_hw_results[i] = 0;
}
populate_results(source_sw_results, seed);
// OPENCL HOST CODE AREA START
......@@ -38,20 +41,16 @@ int main(int argc, char** argv)
OCL_CHECK(err, cl::Program program(context, devices, bins, NULL, &err));
OCL_CHECK(err, cl::Kernel krnl_rnd_gen(program,"rndgen", &err));
short seed = 12345;
// OCL_CHECK(err, cl::Buffer buffer_seed(context,CL_MEM_USE_HOST_PTR | CL_MEM_WRITE_ONLY, sizeof(short), &seed, &err));
OCL_CHECK(err, cl::Buffer buffer_output(context,CL_MEM_USE_HOST_PTR | CL_MEM_WRITE_ONLY, vector_size_bytes, source_hw_results.data(), &err));
// OCL_CHECK(err, err = krnl_rnd_gen.setArg(0, buffer_seed));
OCL_CHECK(err, err = krnl_rnd_gen.setArg(0, buffer_output));
OCL_CHECK(err, err = krnl_rnd_gen.setArg(0, seed));
OCL_CHECK(err, err = krnl_rnd_gen.setArg(1, buffer_output));
std::cout << "* * * START SIMULATION\n";
//OCL_CHECK(err, err = q.enqueueMigrateMemObjects({seed}, 0));
OCL_CHECK(err, err = q.enqueueTask(krnl_rnd_gen));
std::cout << "* * * SIMUlATION DONE\n";
OCL_CHECK(err, err = q.enqueueMigrateMemObjects({buffer_output},CL_MIGRATE_MEM_OBJECT_HOST));
std::cout << "* * * MEMORY OFFLOAD\n";
q.finish();
std::cout << "* * * SIMULATION DONE\n";
// OPENCL HOST CODE AREA END
......@@ -60,10 +59,15 @@ int main(int argc, char** argv)
// Compare the results of the Device to the simulation
std::ofstream fout("data.out");
bool match = true;
for (int i = 0 ; i < DATA_SIZE ; i++){
fout << source_hw_results[i] << ' ';
if (i % 5 == 0)
fout << '\n';
for (int i = 0 ; i < SET_SIZE ; i++){
//if (i % 5 == 0)
// fout << '\n';
//fout << source_hw_results[i] << ' ';
if (source_sw_results[i] != source_hw_results[i]) {
match = false;
fout << source_sw_results[i] << ' ' << source_hw_results[i] << '\n';
}
}
fout.close();
......
src/host.hpp
View file @ 68061b42
......@@ -20,6 +20,7 @@
#include <iostream>
#include <fstream>
#include <CL/cl2.hpp>
#include "defines.hpp"
template <typename T>
struct aligned_allocator
......@@ -84,3 +85,21 @@ char* read_binary_file(const std::string &xclbin_file_name, unsigned &nb)
return buf;
}
void populate_results(std::vector<uint32_t,aligned_allocator<uint32_t>> &v, uint32_t seed) {
uint32_t X, Y;
X = seed;
for (uint32_t i = 0; i < SET_SIZE; i++) {
Y = 0;
for (uint32_t j = 0; j < REG_SIZE; j++) {
uint32_t b1 = (X & (1 << ((j + REG_SIZE-1) % REG_SIZE))) >> ((j + REG_SIZE-1) % REG_SIZE);
uint32_t b2 = (X & (1 << j)) >> j;
uint32_t b3 = (X & (1 << ((j + 1) % REG_SIZE))) >> ((j + 1) % REG_SIZE);
uint32_t r = F1(b1, b2, b3) << j;
Y |= r;
}
v[i] = Y;
X = Y;
}
}
src/rndgen.cpp
View file @ 68061b42
#define REG_SIZE 16
#define SET_SIZE 100
#include <ap_int.h>
#define F1(x, y, z) ((x) ^ ((y) | (z)))
#define F2(x, y, z) (!(x) ^ ((y) | (z)))
#include "defines.hpp"
extern "C" {
void rndgen(
//const ap_int<REG_SIZE> seed,
const int seed,
unsigned int *out
)
{
#pragma HLS INTERFACE m_axi port=out offset=slave bundle=gmem
//#pragma HLS INTERFACE s_axilite port=seed bundle=control
#pragma HLS INTERFACE s_axilite port=seed bundle=control
#pragma HLS INTERFACE s_axilite port=out bundle=control
#pragma HLS INTERFACE s_axilite port=return bundle=control
ap_uint<REG_SIZE> X, Y;
X = 12345;
X = seed;
generator: for (int i = 0; i < SET_SIZE; i++) {
for (int j = 1; j < REG_SIZE - 1; j++)
Y[j] = F2(X[j - 1], X[j], X[j+1]);
Y[j] = F1(X[j - 1], X[j], X[j+1]);
Y[0] = F1(X[REG_SIZE - 1], X[0], X[1]);
Y[REG_SIZE - 1] = F1(X[REG_SIZE - 2], X[REG_SIZE - 1], X[0]);
out[i] = Y.to_int();
out[i] = Y.to_uint();
X = Y;
}
}
......
timeline_kernels.csv 0 → 100644
View file @ 68061b42
Kernel trace events
Device, Binary, Kernel, Compute Unit, Function, Data Type, Index, Start Time (ms), End Time (ms), Value
xilinx_u250_xdma_201830_2-0-rndgen.hw_emu.wcfg 0 → 100755
View file @ 68061b42
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<wvobject type="group" fp_name="HLS_Process_Summary_group">
<obj_property name="label">HLS Process Summary</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="group" fp_name="device_group">
<obj_property name="label">Device &quot;xilinx_u250_xdma_201830_2-0&quot;</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="group" fp_name="bin_group">
<obj_property name="label">Binary Container &quot;rndgen.hw_emu&quot;</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="group" fp_name="kernel_group">
<obj_property name="label">Kernel &quot;rndgen&quot; 1:1:1</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="group" fp_name="cu_group">
<obj_property name="label">Compute Unit: rndgen_1</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<obj_property name="Description_Data">Activity for compute unit rndgen_1</obj_property>
<obj_property name="EnumTransactionColorTable">1=blank</obj_property>
<obj_property name="EnumTransactionValueTable">1=blank;0=Running</obj_property>
<obj_property name="CustomSignalColor">#4DB34D</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<obj_property name="Render_Data">/emu_wrapper/emu_i/rndgen_1/inst/ap_idle</obj_property>
<wvobject type="vbus" fp_name="stall_vbus">
<obj_property name="label">CU Stalls (%)</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="Description_Data">CU Functions that are stalling (%)</obj_property>
<obj_property name="Radix">BITCOUNTRADIX</obj_property>
<obj_property name="SHOWPERCENTCOUNT">true</obj_property>
<obj_property name="ShowWaveText">true</obj_property>
<obj_property name="EnumTransactionColorTable">3=blank</obj_property>
<obj_property name="EnumTransactionValueTable">3=blank</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
<obj_property name="CustomSignalColor">#FF7F27</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
<wvobject db_ref_id="1" type="logic" fp_name="/emu_wrapper/emu_i/rndgen_1/inst//ap_ext_blocking_n">
<obj_property name="label">Top level: External Memory</obj_property>
<obj_property name="Description_Data">Stalls from accessing external memory</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="EnumTransactionColorTable">1=blank</obj_property>
<obj_property name="EnumTransactionValueTable">1=blank;0=stall</obj_property>
<obj_property name="ShowWaveText">false</obj_property>
<obj_property name="CustomSignalColor">#FF7F27</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject db_ref_id="1" type="logic" fp_name="/emu_wrapper/emu_i/rndgen_1/inst//ap_str_blocking_n">
<obj_property name="label">Top level: External Stream</obj_property>
<obj_property name="Description_Data">Stalls from accessing pipes between compute units</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="EnumTransactionColorTable">1=blank</obj_property>
<obj_property name="EnumTransactionValueTable">1=blank;0=stall</obj_property>
<obj_property name="ShowWaveText">false</obj_property>
<obj_property name="CustomSignalColor">#FF7F27</obj_property>
<obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="trans_group">
<obj_property name="label">Data Transfers</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="protoinst" fp_name="/emu_wrapper/emu_i/rndgen_1/m_axi_gmem">
</wvobject>
</wvobject>
</wvobject>
</wvobject>
</wvobject>
</wvobject>
</wave_config>
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