axis_data_fifo_kvs_to_dm_512.veo 4.1 KB
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// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
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// 
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
// 
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// DO NOT MODIFY THIS FILE.

// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
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// IP Revision: 18
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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axis_data_fifo_kvs_to_dm_512 your_instance_name (
  .s_axis_aresetn(s_axis_aresetn),          // input wire s_axis_aresetn
  .m_axis_aresetn(m_axis_aresetn),          // input wire m_axis_aresetn
  .s_axis_aclk(s_axis_aclk),                // input wire s_axis_aclk
  .s_axis_tvalid(s_axis_tvalid),            // input wire s_axis_tvalid
  .s_axis_tready(s_axis_tready),            // output wire s_axis_tready
  .s_axis_tdata(s_axis_tdata),              // input wire [511 : 0] s_axis_tdata
  .s_axis_tkeep(s_axis_tkeep),              // input wire [63 : 0] s_axis_tkeep
  .s_axis_tlast(s_axis_tlast),              // input wire s_axis_tlast
  .m_axis_aclk(m_axis_aclk),                // input wire m_axis_aclk
  .m_axis_tvalid(m_axis_tvalid),            // output wire m_axis_tvalid
  .m_axis_tready(m_axis_tready),            // input wire m_axis_tready
  .m_axis_tdata(m_axis_tdata),              // output wire [511 : 0] m_axis_tdata
  .m_axis_tkeep(m_axis_tkeep),              // output wire [63 : 0] m_axis_tkeep
  .m_axis_tlast(m_axis_tlast),              // output wire m_axis_tlast
  .axis_data_count(axis_data_count),        // output wire [31 : 0] axis_data_count
  .axis_wr_data_count(axis_wr_data_count),  // output wire [31 : 0] axis_wr_data_count
  .axis_rd_data_count(axis_rd_data_count)  // output wire [31 : 0] axis_rd_data_count
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file axis_data_fifo_kvs_to_dm_512.v when simulating
// the core, axis_data_fifo_kvs_to_dm_512. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.