Commit 0e97c14c authored by Claudiu Mihali's avatar Claudiu Mihali
Browse files

Last version of hw before adding decompression

parent 1a001009
...@@ -22,8 +22,6 @@ module ColToRow ...@@ -22,8 +22,6 @@ module ColToRow
input wire output_ready input wire output_ready
); );
//localparam WORD_OFFSET = (MEMORY_WIDTH/8-(VALUE_SIZE_BYTES_NO+VALUE_HEADER_BYTES_NO)) % (COL_WIDTH/8);
reg [$clog2(COL_COUNT)-1:0] current_buffer_engine; reg [$clog2(COL_COUNT)-1:0] current_buffer_engine;
wire [MEMORY_WIDTH:0] buffer_input_data [COL_COUNT-1:0]; wire [MEMORY_WIDTH:0] buffer_input_data [COL_COUNT-1:0];
...@@ -34,7 +32,7 @@ wire [MEMORY_WIDTH:0] buffer_output_data [COL_COUNT-1:0]; ...@@ -34,7 +32,7 @@ wire [MEMORY_WIDTH:0] buffer_output_data [COL_COUNT-1:0];
wire [COL_COUNT-1:0] buffer_output_valid; wire [COL_COUNT-1:0] buffer_output_valid;
reg [COL_COUNT-1:0] buffer_output_ready; reg [COL_COUNT-1:0] buffer_output_ready;
(* mark_debug = "true" *)reg [MEMORY_WIDTH-1:0] colword_buf [COL_COUNT-1:0]; reg [MEMORY_WIDTH-1:0] colword_buf [COL_COUNT-1:0];
reg [COL_COUNT-1:0] colword_last; reg [COL_COUNT-1:0] colword_last;
reg [$clog2(MEMORY_WIDTH)-1:0] colword_addr [COL_COUNT-1:0]; reg [$clog2(MEMORY_WIDTH)-1:0] colword_addr [COL_COUNT-1:0];
...@@ -48,15 +46,14 @@ wire assembled_valid; ...@@ -48,15 +46,14 @@ wire assembled_valid;
wire assembled_last; wire assembled_last;
wire assembled_ready; wire assembled_ready;
(* mark_debug = "true" *)reg [$clog2(COL_WIDTH/8)-1:0] offset [COL_COUNT-1:0]; reg [$clog2(COL_WIDTH/8)-1:0] offset [COL_COUNT-1:0];
integer idx, byte; integer idx, byte;
genvar i; genvar i;
generate generate
for (i=0; i < COL_COUNT; i = i + 1) for (i=0; i < COL_COUNT; i = i + 1)
begin: generateloop begin: generateloop
nukv_fifogen #( nukv_fifogen #(
.DATA_SIZE(MEMORY_WIDTH+1), .DATA_SIZE(MEMORY_WIDTH+1),
.ADDR_BITS(9) .ADDR_BITS(9)
......
...@@ -25,14 +25,14 @@ module MatrixVectorMultiplicationGroup ...@@ -25,14 +25,14 @@ module MatrixVectorMultiplicationGroup
wire rst_n; wire rst_n;
(* mark_debug = "true" *)wire [VECTOR_SIZE*VECTOR_SIZE*ENTRY_SIZE-1:0] matrix_datas[0:MULTIPLICATION_ENGINES_NO-1]; wire [VECTOR_SIZE*VECTOR_SIZE*ENTRY_SIZE-1:0] matrix_datas[0:MULTIPLICATION_ENGINES_NO-1];
(* mark_debug = "true" *)wire [VECTOR_SIZE*ENTRY_SIZE-1:0] vector_datas[0:MULTIPLICATION_ENGINES_NO-1]; wire [VECTOR_SIZE*ENTRY_SIZE-1:0] vector_datas[0:MULTIPLICATION_ENGINES_NO-1];
(* mark_debug = "true" *)wire [MULTIPLICATION_ENGINES_NO-1:0] in_valids; wire [MULTIPLICATION_ENGINES_NO-1:0] in_valids;
(* mark_debug = "true" *)wire [MULTIPLICATION_ENGINES_NO-1:0] in_readys; wire [MULTIPLICATION_ENGINES_NO-1:0] in_readys;
(* mark_debug = "true" *)wire [VECTOR_SIZE*ENTRY_SIZE-1:0] res_datas[0:MULTIPLICATION_ENGINES_NO-1]; wire [VECTOR_SIZE*ENTRY_SIZE-1:0] res_datas[0:MULTIPLICATION_ENGINES_NO-1];
(* mark_debug = "true" *)wire [MULTIPLICATION_ENGINES_NO-1:0] res_valids; wire [MULTIPLICATION_ENGINES_NO-1:0] res_valids;
(* mark_debug = "true" *)wire [MULTIPLICATION_ENGINES_NO-1:0] res_readys; wire [MULTIPLICATION_ENGINES_NO-1:0] res_readys;
reg [$clog2(MULTIPLICATION_ENGINES_NO)-1:0] cur_in_engine_addr = 0; reg [$clog2(MULTIPLICATION_ENGINES_NO)-1:0] cur_in_engine_addr = 0;
reg [$clog2(MULTIPLICATION_ENGINES_NO)-1:0] cur_out_engine_addr = 0; reg [$clog2(MULTIPLICATION_ENGINES_NO)-1:0] cur_out_engine_addr = 0;
...@@ -86,7 +86,7 @@ assign out_valid = res_valids[cur_out_engine_addr]; ...@@ -86,7 +86,7 @@ assign out_valid = res_valids[cur_out_engine_addr];
nukv_fifogen #( nukv_fifogen #(
.DATA_SIZE(8*VALUE_SIZE_BYTES_NO), .DATA_SIZE(8*VALUE_SIZE_BYTES_NO),
.ADDR_BITS(4) .ADDR_BITS(5)
) fifo_output ( ) fifo_output (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
......
...@@ -43,6 +43,43 @@ module nukv_Privacy_Pipeline ...@@ -43,6 +43,43 @@ module nukv_Privacy_Pipeline
); );
reg [1:0] skip_blocks;
reg first_cnt_word;
(* mark_debug = "true" *)reg [63:0] cnt_valid;
(* mark_debug = "true" *)reg [63:0] cnt_last;
always @(posedge clk) begin
if (rst == 1) begin
cnt_valid <= 0;
cnt_last <= 0;
skip_blocks <= 0;
first_cnt_word <= 1;
end else begin
if (skip_blocks < 3) begin
if (output_valid == 1 && output_ready == 1 && output_last == 1) begin
skip_blocks <= skip_blocks + 1;
end
end else begin
if (first_cnt_word == 1) begin
if (output_valid == 1 && output_ready == 1) begin
first_cnt_word <= 0;
cnt_valid <= 1;
if (output_last == 1) begin
cnt_last <= 1;
end
end
end else begin
if (output_valid == 1 && output_ready == 1) begin
cnt_valid <= cnt_valid + 1;
if (output_last == 1) begin
cnt_last <= cnt_last + 1;
end
end
end
end
end
end
wire [MEMORY_WIDTH-1:0] seg_data; wire [MEMORY_WIDTH-1:0] seg_data;
wire seg_valid; wire seg_valid;
wire seg_last; wire seg_last;
...@@ -150,7 +187,7 @@ module nukv_Privacy_Pipeline ...@@ -150,7 +187,7 @@ module nukv_Privacy_Pipeline
nukv_fifogen #( nukv_fifogen #(
.DATA_SIZE(MEMORY_WIDTH+1), .DATA_SIZE(MEMORY_WIDTH+1),
.ADDR_BITS(8) .ADDR_BITS(10)
) fifo_bypass ( ) fifo_bypass (
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
......
...@@ -377,7 +377,7 @@ end component; ...@@ -377,7 +377,7 @@ end component;
signal mrdel_data : std_logic_vector(64*512-1 downto 0); signal mrdel_data : std_logic_vector(64*512-1 downto 0);
signal mrdel_empty : std_logic_vector(63 downto 0); signal mrdel_empty : std_logic_vector(63 downto 0);
signal counter: std_logic_vector(31 downto 0) := (others => '0'); signal count : std_logic_vector(63 downto 0) := (others => '0');
begin begin
...@@ -671,7 +671,7 @@ mockmem_bitmap : entity work.kvs_tbDRAM_Module ...@@ -671,7 +671,7 @@ mockmem_bitmap : entity work.kvs_tbDRAM_Module
else else
counter <= counter + 1; count <= count + 1;
mrdel_data(64*512-1 downto 63*512) <= d_rd_data; mrdel_data(64*512-1 downto 63*512) <= d_rd_data;
mrdel_empty(63) <= d_rd_data_empty; mrdel_empty(63) <= d_rd_data_empty;
......
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