Commit 11feb509 authored by Zsolt István's avatar Zsolt István
Browse files

working towards example design with a columnt-to-row converter

parent ac91f300
......@@ -30,8 +30,7 @@ module muu_Top_Module_LMem #(
parameter KEY_WIDTH = 64,
parameter HASHTABLE_MEM_SIZE = 20,
parameter VALUESTORE_MEM_SIZE = 24,
parameter FILTER_PRED_CNT = 0,
parameter FILTER_REGEX_PARA = 0,
parameter PRIVACY_ENABLED = 1,
parameter IS_SIM = 0,
parameter USER_BITS = 3
)(
......@@ -151,8 +150,6 @@ parameter HASH_WIDTH = 32;
parameter SUPPORT_SCANS = 0;
parameter FILTER_ENABLED_NUM = FILTER_REGEX_PARA + FILTER_PRED_CNT;
wire [31:0] rdcmd_data;
wire rdcmd_valid;
wire rdcmd_stall;
......@@ -1716,7 +1713,7 @@ wire cond_ready;
wire cond_drop;
generate
if (FILTER_ENABLED_NUM==0) begin
if (PRIVACY_ENABLED==0) begin
//no filters in the project, cuts out whole part
assign cond_valid = predconf_b_valid;
assign cond_drop = 0;
......@@ -1730,41 +1727,28 @@ generate
else begin
//need to wire in filters
nukv_Predicate_Eval_Pipeline_v2
#(.SUPPORT_SCANS(SUPPORT_SCANS),
.PIPE_DEPTH(FILTER_PRED_CNT),
.META_WIDTH(EXT_META_WIDTH)
) pred_eval_pipe (
nukv_Privacy_Pipeline priv_pipe (
.clk(clk),
.rst(rst),
.pred_data(predconf_b_fulldata[NET_META_WIDTH+MEMORY_WIDTH : 1]),
.pred_data(predconf_b_fulldata[1]),
.pred_valid(predconf_b_valid),
.pred_ready(predconf_b_ready),
.pred_scan((SUPPORT_SCANS==1) ? predconf_b_fulldata[0] : 0),
.value_data(value_read_data_buf),
.value_last(0),
.value_drop(0),
.value_valid(value_read_valid_buf),
.value_ready(value_read_ready_buf),
.output_valid(value_frompipe_valid),
.output_ready(value_frompipe_ready),
.output_data(value_frompipe_data),
.output_last(value_frompipe_last),
.output_drop(value_frompipe_drop),
.scan_on_outside(scan_mode_on),
.cmd_valid(pe_cmd_valid),
.cmd_length(pe_cmd_data),
.cmd_meta(pe_cmd_meta),
.cmd_ready(pe_cmd_ready)
.output_last(value_frompipe_last)
);
assign value_frompipe_drop = 0;
nukv_fifogen #(
.DATA_SIZE(MEMORY_WIDTH),
......
module ColToRow #(
parameter COL_BITS = 2,
parameter COL_COUNT = 3,
parameter CNT_SKIP_WORDS = 0,
parameter EQUAL_LENGTH_COMP = 1
)
(
input wire clk,
input wire rst,
input wire [511:0] input_data,
input wire input_valid,
input wire input_last,
output wire input_ready,
output wire [COL_COUNT*32-1:0] output_data,
output wire output_valid,
output wire output_last,
input wire output_ready
);
reg [512:0] buffer_input_data [COL_COUNT-1:0];
wire [COL_COUNT-1:0] buffer_input_hasdata;
wire [COL_COUNT-1:0] buffer_input_almfull;
wire [COL_COUNT-1:0] buffer_input_notfull;
reg [COL_COUNT-1:0] buffer_input_enable;
wire [512:0] buffer_output_data [COL_COUNT-1:0];
wire [COL_COUNT-1:0] buffer_output_valid;
wire buffer_output_ready;
reg[3:0] assembled_pos;
wire [32*COL_COUNT-1:0] assembled_data;
wire assembled_last;
wire[COL_COUNT-1:0] assembled_last_pre;
wire assembled_valid;
wire assembled_ready;
reg [COL_BITS-1:0] current_buffer_engine;
reg buffer_inputbuffer_ok;
reg buffer_inputbuffer_pre;
assign input_ready = (buffer_inputbuffer_ok);
reg rstBuf;
integer x;
reg first_word;
always @(posedge clk) begin
rstBuf <= rst;
if (rst) begin
current_buffer_engine <= 0;
buffer_input_enable <= 0;
buffer_inputbuffer_ok <= 0;
buffer_inputbuffer_pre <= 0;
assembled_pos <= CNT_SKIP_WORDS;
first_word <= 1;
end
else begin
buffer_input_enable <= 0;
buffer_inputbuffer_pre <= (buffer_input_notfull == {COL_COUNT{1'b1}} ? 1 : 0) && (buffer_input_almfull == 0 ? 1 : 0);
buffer_inputbuffer_ok <= buffer_inputbuffer_pre;
if (input_ready==1 && input_valid==1) begin
buffer_input_data[current_buffer_engine] <= {input_last, input_data};
buffer_input_enable[current_buffer_engine] <= 1;
if (input_last==1) begin
if (current_buffer_engine==COL_COUNT-1) begin
current_buffer_engine <= 0;
end else begin
current_buffer_engine <= current_buffer_engine +1;
end
end
end
if (assembled_valid==1 && assembled_ready==1) begin
assembled_pos <= assembled_pos+1;
first_word <= 0;
if (assembled_last==1) begin
assembled_pos <= CNT_SKIP_WORDS;
first_word <= 1;
end
end
end
end
wire [31:0] sum;
genvar X;
generate
if (EQUAL_LENGTH_COMP==1) begin
assign sum=buffer_output_data[0][31:0]+buffer_output_data[1][31:0]+buffer_output_data[2][31:0];
end
for (X=0; X < COL_COUNT; X=X+1)
begin: generateloop
nukv_fifogen #(
.DATA_SIZE(513),
.ADDR_BITS(9)
)
fifo_values (
.clk(clk),
.rst(rstBuf),
.s_axis_tdata(buffer_input_data[X]),
.s_axis_tvalid(buffer_input_enable[X]),
.s_axis_tready(buffer_input_notfull[X]),
.s_axis_talmostfull(buffer_input_almfull[X]),
.m_axis_tdata(buffer_output_data[X][512:0]),
.m_axis_tvalid(buffer_output_valid[X]),
.m_axis_tready(buffer_output_ready)
);
assign assembled_data[X*32 +: 32] = (assembled_pos==0 && first_word==1 && EQUAL_LENGTH_COMP==1) ? sum : buffer_output_data[X][assembled_pos*32 +: 32];
assign assembled_last_pre[X] = buffer_output_data[X][512];
end
endgenerate
assign assembled_valid = (buffer_output_valid == {COL_COUNT{1'b1}}) ? 1 : 0;
assign buffer_output_ready = (assembled_pos==15) ? assembled_ready : 0;
assign assembled_last = (assembled_pos==15 && assembled_last_pre=={COL_COUNT{1'b1}}) ? 1 : 0;
nukv_fifogen #(
.DATA_SIZE(COL_COUNT*32+1),
.ADDR_BITS(4)
) fifo_output (
.clk(clk),
.rst(rstBuf),
.s_axis_tdata({assembled_last,assembled_data}),
.s_axis_tvalid(assembled_valid),
.s_axis_tready(assembled_ready),
.s_axis_talmostfull(),
.m_axis_tdata({output_last,output_data}),
.m_axis_tvalid(output_valid),
.m_axis_tready(output_ready)
);
endmodule
\ No newline at end of file
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Privacy_Pipeline #(
parameter MEMORY_WIDTH = 512
)
(
// Clock
input wire clk,
input wire rst,
input wire pred_data,
input wire pred_valid,
output wire pred_ready,
input wire [MEMORY_WIDTH-1:0] value_data,
input wire value_valid,
output wire value_ready,
output wire [MEMORY_WIDTH-1:0] output_data,
output wire output_valid,
output wire output_last,
input wire output_ready
);
wire[MEMORY_WIDTH-1:0] seg_data;
wire seg_valid;
wire seg_last;
wire seg_ready;
wire ic_data;
wire ic_valid;
wire ic_valid_masked;
wire ic_ready;
wire ic_ready_fifo;
wire oc_data;
wire oc_valid;
wire oc_ready;
wire[MEMORY_WIDTH-1:0] imed_data [1:0];
wire[1:0] imed_valid;
wire[1:0] imed_last;
wire[1:0] imed_ready;
wire[MEMORY_WIDTH-1:0] omed_data [1:0];
wire[1:0] omed_valid;
wire[1:0] omed_last;
wire[1:0] omed_ready;
assign pred_ready = 1;
nukv_fifogen #(
.DATA_SIZE(8),
.ADDR_BITS(5)
) fifo_input_choice (
.clk(clk),
.rst(rst),
.s_axis_tdata(pred_data),
.s_axis_tvalid(pred_valid),
.s_axis_tready(pred_rady),
.s_axis_talmostfull(),
.m_axis_tdata(ic_data),
.m_axis_tvalid(ic_valid),
.m_axis_tready(ic_ready)
);
assign ic_ready = ic_ready_fifo & seg_valid & seg_last & seg_ready;
assign ic_valid_masked = ic_valid & ic_ready;
nukv_Value_Segmenter segmenter (
.clk(clk),
.rst(rst),
.value_data(value_data),
.value_valid(value_valid),
.value_ready(value_ready),
.output_data(seg_data),
.output_last(seg_last),
.output_valid(seg_valid),
.output_ready(seg_ready)
);
assign imed_data[0] = seg_data;
assign imed_last[0] = seg_last;
assign imed_data[1] = seg_data;
assign imed_last[1] = seg_last;
assign seg_ready = ic_valid==1 ? imed_ready[ic_data] : 0;
assign imed_valid[0] = ic_valid==1 && ic_data==0 ? seg_valid : 0;
assign imed_valid[1] = ic_valid==1 && ic_data==1 ? seg_valid : 0;
nukv_fifogen #(
.DATA_SIZE(513),
.ADDR_BITS(8)
) fifo_bypass (
.clk(clk),
.rst(rst),
.s_axis_tdata({imed_last[0],imed_data[0]}),
.s_axis_tvalid(imed_valid[0]),
.s_axis_tready(imed_ready[0]),
.s_axis_talmostfull(),
.m_axis_tdata({omed_last[0],omed_data[0]}),
.m_axis_tvalid(omed_valid[0]),
.m_axis_tready(omed_ready[0])
);
nukv_Rotation_Module rotation_perturb (
.clk(clk),
.rst(rst),
.input_data(imed_data[1]),
.input_valid(imed_valid[1]),
.input_ready(imed_ready[1]),
.input_last(imed_last[1]),
.output_data(omed_data[1]),
.output_valid(omed_valid[1]),
.output_ready(omed_ready[1]),
.output_last(omed_last[1])
);
nukv_fifogen #(
.DATA_SIZE(8),
.ADDR_BITS(5)
) fifo_output_choice (
.clk(clk),
.rst(rst),
.s_axis_tdata(ic_data),
.s_axis_tvalid(ic_valid_masked),
.s_axis_tready(ic_ready_fifo),
.s_axis_talmostfull(),
.m_axis_tdata(oc_data),
.m_axis_tvalid(oc_valid),
.m_axis_tready(oc_ready)
);
assign oc_ready = oc_valid & omed_valid[oc_data] & omed_last[oc_data] & output_ready;
assign output_data = oc_valid==1 ? omed_data[oc_data] : 0;
assign output_last = oc_valid==1 ? omed_last[oc_data] : 0;
assign output_valid = oc_valid==1 ? omed_valid[oc_data] : 0;
assign omed_ready[0] = oc_valid==1 && oc_data==0 ? output_ready : 0;
assign omed_ready[1] = oc_valid==1 && oc_data==1 ? output_ready : 0;
endmodule
\ No newline at end of file
module nukv_Rotation_Module
(
input wire clk,
input wire rst,
input wire [511:0] input_data,
input wire input_valid,
input wire input_last,
output wire input_ready,
output wire [511:0] output_data,
output wire output_valid,
output wire output_last,
input wire output_ready
);
reg[2:0] state;
wire[511:0] ctr_data;
wire ctr_valid;
wire ctr_ready;
wire ctr_last;
reg[511:0] alt_data;
reg alt_valid;
reg alt_last;
ColToRow #(
.EQUAL_LENGTH_COMP(1)
) rotation_perturb (
.clk(clk),
.rst(rst),
.input_data(input_data),
.input_valid(input_valid),
.input_ready(input_ready),
.input_last(input_last),
.output_data(ctr_data),
.output_valid(ctr_valid),
.output_ready(ctr_ready),
.output_last(ctr_last)
);
assign output_valid = state==0 ? ctr_valid : alt_valid;
assign output_data = state==0 ? ctr_data : alt_data;
assign output_last = state==0 ? ctr_last : alt_last;
assign ctr_ready = state==0 ? output_ready : 0;
always @(posedge clk) begin
if(rst) begin
alt_data <= {504'b0, 8'h08};
alt_last <= 1;
alt_valid <= 1;
state <= 0;
end else begin
case (state)
0: begin
if (ctr_valid==1 && output_ready==1 && ctr_last==1) begin
state <= state+1;
end
end
1: begin
if (alt_valid==1 && output_ready==1 && alt_last==1) begin
state <= state+1;
end
end
2: begin
if (alt_valid==1 && output_ready==1 && alt_last==1) begin
state <= 0;
end
end
default : /* default */;
endcase
end
end
endmodule;
\ No newline at end of file
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_Value_Segmenter #(
parameter MEMORY_WIDTH = 512
)
(
// Clock
input wire clk,
input wire rst,
input wire [MEMORY_WIDTH-1:0] value_data,
input wire value_valid,
output wire value_ready,
output wire [MEMORY_WIDTH-1:0] output_data,
output wire output_valid,
output wire output_last,
input wire output_ready
);
localparam[2:0]
ST_IDLE = 0,
ST_READING = 1,
ST_LAST = 2;
reg[2:0] state;
reg out_valid;
wire out_ready;
reg[MEMORY_WIDTH-1:0] out_data;
reg out_last;
wire out_b_valid;
wire out_b_ready;
wire[MEMORY_WIDTH-1:0] out_b_data;
wire out_b_last;
reg[15:0] curr_offset;
reg[15:0] total_length;
reg[15:0] curr_offset_p128;
wire enter_ifs;
reg readInValue;
wire stateBasedReady = (state==ST_IDLE) ? 1 : readInValue;
assign value_ready = (stateBasedReady & out_ready);
reg[MEMORY_WIDTH-1:0] slice_full;
reg slice_valid;
integer xx;
always @(posedge clk) begin
if (rst) begin
// reset
state <= ST_IDLE;
out_valid <= 0;
out_last <= 0;
readInValue <= 0;
slice_valid <= 0;
end
else begin
if (out_valid==1 && out_ready==1) begin
out_valid <= 0;
out_last <= 0;
end
if (slice_valid==1 && out_ready==1) begin
slice_valid <= 0;
end
if (value_valid==1 && value_ready==1) begin
slice_full <= value_data;
slice_valid <= 1;
end
case (state)
ST_IDLE: begin
//readInValue <= 1;
if (value_valid==1 && out_ready==1) begin
curr_offset <= 0;
curr_offset_p128 <= 128;
total_length <= value_data[15:0];
state <= ST_READING;
readInValue <= 1;
if (value_data[15:0] <= 64) begin