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Commit 5e69713b authored by Zsolt István's avatar Zsolt István
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added IP files to get a wokring copy

parent 88c064ce
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hw/constraints/vcu1525.xdc
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hw/ip/vcu1525/arp_server_subnet_ip/arp_server_subnet_ip.veo 0 → 100644
View file @ 5e69713b
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: ethz.systems:hls:arp_server_subnet:1.0
// IP Revision: 1901302202
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
arp_server_subnet_ip your_instance_name (
.myMacAddress_V(myMacAddress_V), // input wire [47 : 0] myMacAddress_V
.myIpAddress_V(myIpAddress_V), // input wire [31 : 0] myIpAddress_V
.m_axis_TVALID(m_axis_TVALID), // output wire m_axis_TVALID
.m_axis_TREADY(m_axis_TREADY), // input wire m_axis_TREADY
.m_axis_TDATA(m_axis_TDATA), // output wire [63 : 0] m_axis_TDATA
.m_axis_TKEEP(m_axis_TKEEP), // output wire [7 : 0] m_axis_TKEEP
.m_axis_TLAST(m_axis_TLAST), // output wire [0 : 0] m_axis_TLAST
.m_axis_arp_lookup_reply_TVALID(m_axis_arp_lookup_reply_TVALID), // output wire m_axis_arp_lookup_reply_TVALID
.m_axis_arp_lookup_reply_TREADY(m_axis_arp_lookup_reply_TREADY), // input wire m_axis_arp_lookup_reply_TREADY
.m_axis_arp_lookup_reply_TDATA(m_axis_arp_lookup_reply_TDATA), // output wire [55 : 0] m_axis_arp_lookup_reply_TDATA
.s_axis_TVALID(s_axis_TVALID), // input wire s_axis_TVALID
.s_axis_TREADY(s_axis_TREADY), // output wire s_axis_TREADY
.s_axis_TDATA(s_axis_TDATA), // input wire [63 : 0] s_axis_TDATA
.s_axis_TKEEP(s_axis_TKEEP), // input wire [7 : 0] s_axis_TKEEP
.s_axis_TLAST(s_axis_TLAST), // input wire [0 : 0] s_axis_TLAST
.s_axis_arp_lookup_request_TVALID(s_axis_arp_lookup_request_TVALID), // input wire s_axis_arp_lookup_request_TVALID
.s_axis_arp_lookup_request_TREADY(s_axis_arp_lookup_request_TREADY), // output wire s_axis_arp_lookup_request_TREADY
.s_axis_arp_lookup_request_TDATA(s_axis_arp_lookup_request_TDATA), // input wire [31 : 0] s_axis_arp_lookup_request_TDATA
.aclk(aclk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
hw/ip/vcu1525/arp_server_subnet_ip/arp_server_subnet_ip.xci 0 → 100644
View file @ 5e69713b
<?xml version="1.0" encoding="UTF-8"?>
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hw/ip/vcu1525/axis_data_fifo_64_cc/axis_data_fifo_64_cc.veo 0 → 100644
View file @ 5e69713b
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 18
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axis_data_fifo_64_cc your_instance_name (
.s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn
.m_axis_aresetn(m_axis_aresetn), // input wire m_axis_aresetn
.s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
.s_axis_tdata(s_axis_tdata), // input wire [63 : 0] s_axis_tdata
.s_axis_tkeep(s_axis_tkeep), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
.m_axis_aclk(m_axis_aclk), // input wire m_axis_aclk
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
.m_axis_tdata(m_axis_tdata), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep(m_axis_tkeep), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast), // output wire m_axis_tlast
.axis_data_count(axis_data_count), // output wire [31 : 0] axis_data_count
.axis_wr_data_count(axis_wr_data_count), // output wire [31 : 0] axis_wr_data_count
.axis_rd_data_count(axis_rd_data_count) // output wire [31 : 0] axis_rd_data_count
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file axis_data_fifo_64_cc.v when simulating
// the core, axis_data_fifo_64_cc. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
hw/ip/vcu1525/axis_data_fifo_64_cc/axis_data_fifo_64_cc.xci 0 → 100644
View file @ 5e69713b
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hw/ip/vcu1525/axis_data_fifo_64_d2048/axis_data_fifo_64_d2048.veo 0 → 100644
View file @ 5e69713b
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 18
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axis_data_fifo_64_d2048 your_instance_name (
.s_axis_aresetn(s_axis_aresetn), // input wire s_axis_aresetn
.s_axis_aclk(s_axis_aclk), // input wire s_axis_aclk
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
.s_axis_tdata(s_axis_tdata), // input wire [63 : 0] s_axis_tdata
.s_axis_tkeep(s_axis_tkeep), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
.m_axis_tdata(m_axis_tdata), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep(m_axis_tkeep), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast(m_axis_tlast), // output wire m_axis_tlast
.axis_data_count(axis_data_count), // output wire [31 : 0] axis_data_count
.axis_wr_data_count(axis_wr_data_count), // output wire [31 : 0] axis_wr_data_count
.axis_rd_data_count(axis_rd_data_count) // output wire [31 : 0] axis_rd_data_count
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file axis_data_fifo_64_d2048.v when simulating
// the core, axis_data_fifo_64_d2048. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
hw/ip/vcu1525/axis_data_fifo_64_d2048/axis_data_fifo_64_d2048.xci 0 → 100644
View file @ 5e69713b
<?xml version="1.0" encoding="UTF-8"?>
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