Commit 6056428e authored by Zsolt István's avatar Zsolt István
Browse files

bugfixing in session management -- segmented large packets created issues before

parent a35df4e0
// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
......@@ -55,15 +55,18 @@
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
zk_fifo_128x1024 your_instance_name (
.s_aclk(s_aclk), // input wire s_aclk
.s_aresetn(s_aresetn), // input wire s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
.s_axis_tdata(s_axis_tdata), // input wire [127 : 0] s_axis_tdata
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
.m_axis_tdata(m_axis_tdata), // output wire [127 : 0] m_axis_tdata
.axis_prog_full(axis_prog_full) // output wire axis_prog_full
.s_aclk(s_aclk), // input wire s_aclk
.s_aresetn(s_aresetn), // input wire s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(s_axis_tready), // output wire s_axis_tready
.s_axis_tdata(s_axis_tdata), // input wire [127 : 0] s_axis_tdata
.s_axis_tlast(s_axis_tlast), // input wire s_axis_tlast
.m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid
.m_axis_tready(m_axis_tready), // input wire m_axis_tready
.m_axis_tdata(m_axis_tdata), // output wire [127 : 0] m_axis_tdata
.m_axis_tlast(m_axis_tlast), // output wire m_axis_tlast
.axis_data_count(axis_data_count), // output wire [10 : 0] axis_data_count
.axis_prog_full(axis_prog_full) // output wire axis_prog_full
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
......
......@@ -81,10 +81,13 @@ architecture beh of muu_session_Top is
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
axis_prog_full : out std_logic
m_axis_tlast : out std_logic;
axis_prog_full : out std_logic;
axis_data_count : out std_logic_vector(10 downto 0)
);
END component;
......@@ -125,6 +128,7 @@ architecture beh of muu_session_Top is
type ARRAY128 is array (BUFFER_COUNT - 1 downto 0) of std_logic_vector(127 downto 0);
type ARRAY16 is array (BUFFER_COUNT - 1 downto 0) of std_logic_vector(15 downto 0);
type ARRAY11 is array (BUFFER_COUNT - 1 downto 0) of std_logic_vector(10 downto 0);
signal eventValid : std_logic;
signal eventReady : std_logic;
......@@ -156,8 +160,10 @@ architecture beh of muu_session_Top is
signal bufferOutValid : std_logic_vector(BUFFER_COUNT - 1 downto 0);
signal bufferOutReady : std_logic_vector(BUFFER_COUNT - 1 downto 0);
signal bufferOutLast : std_logic_vector(BUFFER_COUNT - 1 downto 0);
signal bufferOutDataArr : ARRAY128;
signal bufferOutDataFolded : ARRAY128;
signal bufferOutDataFolded : ARRAY128;
signal bufferOutOccup : ARRAY11;
signal packetReady : std_logic;
signal waitingFirst : std_logic;
......@@ -165,6 +171,11 @@ architecture beh of muu_session_Top is
signal waitLocation : std_logic;
signal haveLocation : std_logic;
signal locationMask : std_logic_vector(BUFFER_COUNT - 1 downto 0);
signal locationPending : ARRAY16;
signal packetLengthField : std_logic_vector(15 downto 0);
signal packetInnerLast : std_logic_vector(BUFFER_COUNT-1 downto 0);
signal packetInnerLastD1 : std_logic_vector(BUFFER_COUNT-1 downto 0);
signal bufferSelectMask : std_logic_vector(BUFFER_COUNT - 1 downto 0);
signal bufferEmptyChange : std_logic;
......@@ -197,6 +208,12 @@ architecture beh of muu_session_Top is
signal errorLength : std_logic;
signal stopped : std_logic;
ATTRIBUTE MARK_DEBUG : string;
ATTRIBUTE MARK_DEBUG of locationPending: SIGNAL IS "TRUE";
ATTRIBUTE MARK_DEBUG of packetInnerLast: SIGNAL IS "TRUE";
begin
......@@ -280,6 +297,12 @@ begin
haveLocation <= '0';
waitLocation <= '0';
locationMask <= (others => '0');
packetInnerLast <= (others => '0');
packetInnerLastD1 <= (others => '0');
for X in 0 to BUFFER_COUNT - 1 loop
locationPending(X) <= (others => '0');
end loop;
else
if (packet_last = '1' and packet_valid = '1' and packetReady = '1') then
......@@ -290,6 +313,7 @@ begin
if (waitingFirst = '1' and packet_valid = '1') then
waitingFirst <= '0';
packetLengthField <= packet_data(15+32 downto 32)+2;
end if;
if (dataFirstCycle = '1') then
......@@ -300,10 +324,48 @@ begin
locationMask(BUFFER_COUNT - 1 downto 0) <= bufferSelectMask;
waitLocation <= '0';
haveLocation <= '1';
for X in 0 to BUFFER_COUNT - 1 loop
if (bufferSelectMask(X) = '1' and locationPending(X)=0) then
locationPending(X) <= packetLengthField;
end if;
end loop;
end if;
if (packet_valid='1' and packetReady='1') then
for X in 0 to BUFFER_COUNT - 1 loop
if (locationMask(X) = '1') then
packetInnerLastD1(X) <= packetInnerLast(X);
packetInnerLast(X) <= '0';
if (locationPending(X)/=0) then
locationPending(X) <= locationPending(X)-1;
end if;
if (locationPending(X)=2) then
packetInnerLast(X) <= '1';
end if;
if (packetInnerLastD1(X) = '1' and packet_data(15 downto 0)="1111111111111111") then
locationPending(X) <= packet_data(15+32 downto 32)+1;
end if;
end if;
end loop;
end if;
bufferEmptyChange <= '0';
bufferEmpty <= not bufferOutValid;
for X in 0 to BUFFER_COUNT - 1 loop
if (bufferOutOccup(X)=0) then
bufferEmpty(X) <= '1';
else
bufferEmpty(X) <= '0';
end if;
end loop;
if (selbufNext = '1') then
bufferEmptyD1 <= bufferEmpty;
......@@ -350,9 +412,9 @@ begin
gen_bufs_i : zk_fifo_128x1024
port map(
clk, rstn,
bufferInValid(X), bufferInReady(X), bufferInData,
bufferOutValid(X), bufferOutReady(X), bufferOutDataArr(X),
bufferInProgFull(X)
bufferInValid(X), bufferInReady(X), bufferInData, packetInnerLast(X),
bufferOutValid(X), bufferOutReady(X), bufferOutDataArr(X), bufferOutLast(X),
bufferInProgFull(X), bufferOutOccup(X)
);
end generate gen_bufs;
......
......@@ -387,7 +387,7 @@ module muu_TopWrapper #(
nukv_fifogen #(
.DATA_SIZE(65),
.ADDR_BITS(5)
.ADDR_BITS(8)
) input_firstword_fifo_inst (
.clk(aclk),
.rst(reset),
......@@ -405,7 +405,7 @@ module muu_TopWrapper #(
wire[127:0] debug_sess;
wire[127:0] debug_sess;
muu_session_Top #(
.USER_BITS(USER_BITS)
) muuSessionMngr (
......@@ -436,7 +436,7 @@ module muu_TopWrapper #(
.out_meta(sesspackMeta),
.out_userid(sesspackUser),
.debug_out()
.debug_out(debug_sess)
);
assign splitPreValid = sesspackValid;
......
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