Commit 68c284e1 authored by Zsolt István's avatar Zsolt István
Browse files

working towards linerate POC

parent e4cf0823
......@@ -31,8 +31,8 @@ module muu_Dedup_Hashers
input hash_ready
);
parameter HASH_COUNT_BITS = 3;
parameter MAX_HASH_ENGINES = 8;
parameter HASH_COUNT_BITS = 4;
parameter MAX_HASH_ENGINES = 9;
wire [512:0] hash_input_data [MAX_HASH_ENGINES-1:0];
reg [512:0] hash_input_prebuf [MAX_HASH_ENGINES-1:0];
......
......@@ -170,23 +170,23 @@ wire [39:0] upd_wrcmd_data;
wire upd_wrcmd_ready;
wire [15:0] mreq_data;
wire mreq_valid;
wire mreq_ready;
(* mark_debug = "true" *)wire mreq_valid;
(* mark_debug = "true" *)wire mreq_ready;
wire [15:0] mreq_data_b;
wire mreq_valid_b;
wire mreq_ready_b;
wire [31:0] malloc_data;
wire malloc_valid;
wire malloc_failed;
wire malloc_ready;
(* mark_debug = "true" *)wire malloc_valid;
(* mark_debug = "true" *)wire malloc_failed;
(* mark_debug = "true" *)wire malloc_ready;
wire [31:0] free_data;
wire [15:0] free_size;
wire free_valid;
wire free_ready;
wire free_wipe;
(* mark_debug = "true" *)wire free_valid;
(* mark_debug = "true" *)wire free_ready;
(* mark_debug = "true" *)wire free_wipe;
wire [31:0] malloc_data_b;
wire [31+1:0] malloc_data_full_b;
......@@ -203,12 +203,12 @@ wire free_wipe_b;
wire [63:0] key_data;
wire key_last;
wire key_valid;
wire key_ready;
(* mark_debug = "true" *)wire key_valid;
(* mark_debug = "true" *)wire key_ready;
wire [EXT_META_WIDTH-1:0] meta_data;
wire meta_valid;
wire meta_ready;
(* mark_debug = "true" *)wire meta_valid;
(* mark_debug = "true" *)wire meta_ready;
wire [USER_BITS+63:0] tohash_data;
......@@ -276,8 +276,8 @@ wire fromset_valid;
wire fromset_ready;
wire [KEY_WIDTH+EXT_META_WIDTH+HEADER_WIDTH-1:0] fromset_b_data;
wire fromset_b_valid;
wire fromset_b_ready;
(* mark_debug = "true" *)wire fromset_b_valid;
(* mark_debug = "true" *)wire fromset_b_ready;
wire [KEY_WIDTH+EXT_META_WIDTH+DOUBLEHASH_WIDTH-1:0] towrite_data;
wire towrite_valid;
......@@ -411,9 +411,9 @@ reg sAxisSecond;
wire [127:0] in_axis_tdata;
wire [USER_BITS-1:0] in_axis_tuserid;
wire in_axis_tvalid;
wire in_axis_tlast;
wire in_axis_tready;
(* mark_debug = "true" *)wire in_axis_tvalid;
(* mark_debug = "true" *)wire in_axis_tlast;
(* mark_debug = "true" *)wire in_axis_tready;
reg decruserValid;
reg[7:0] decruserID;
......@@ -663,13 +663,13 @@ nukv_fifogen #(
);
wire[511:0] value_prehash_data;
wire value_prehash_last;
wire value_prehash_valid;
wire value_prehash_ready;
(* mark_debug = "true" *)wire value_prehash_last;
(* mark_debug = "true" *)wire value_prehash_valid;
(* mark_debug = "true" *)wire value_prehash_ready;
wire[63:0] value_hash_data;
wire value_hash_valid;
wire value_hash_ready;
(* mark_debug = "true" *)wire value_hash_valid;
(* mark_debug = "true" *)wire value_hash_ready;
nukv_fifogen #(
.DATA_SIZE(513),
......@@ -692,7 +692,6 @@ muu_Dedup_Hashers sha_engines
(
.clk(clk),
.rst(rst),
.mode(1),
.input_data(value_prehash_data),
.input_last(value_prehash_last),
.input_valid(value_prehash_valid),
......
......@@ -256,9 +256,9 @@ module muu_TopWrapper #(
wire [127:0] toKvsData;
wire [USER_BITS-1:0] toKvsUserId;
wire fromKvsValid;
wire fromKvsReady;
wire fromKvsLast;
(* mark_debug = "true" *)wire fromKvsValid;
(* mark_debug = "true" *)wire fromKvsReady;
(* mark_debug = "true" *)wire fromKvsLast;
wire [127:0] fromKvsData;
wire [USER_BITS-1:0] fromKvsUser;
......@@ -308,9 +308,9 @@ module muu_TopWrapper #(
wire splitPreReady;
wire [3+128:0] splitPreDataMerged;
wire splitInValid;
wire splitInLast;
wire splitInReady;
(* mark_debug = "true" *)wire splitInValid;
(* mark_debug = "true" *)wire splitInLast;
(* mark_debug = "true" *)wire splitInReady;
wire [63:0] splitInData;
wire [63:0] splitInMeta;
wire [128+USER_BITS:0] splitInDataMerged;
......
......@@ -839,7 +839,7 @@ ip_handler_ip ip_handler_inst (
.s_axis_raw_TKEEP(AXI_S_Stream_TKEEP), // input [7 : 0] AXI4Stream_S_TSTRB
.s_axis_raw_TLAST(AXI_S_Stream_TLAST), // input [0 : 0] AXI4Stream_S_TLAST
.regIpAddress_V(iph_ip_address),
.myIpAddress_V(iph_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
......@@ -1010,8 +1010,8 @@ arp_server_subnet_ip arp_server_inst(
.s_axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.s_axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
.regMacAddress_V(arp_mac_address),
.regIpAddress_V(arp_ip_address),
.myMacAddress_V(arp_mac_address),
.myIpAddress_V(arp_ip_address),
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
......
......@@ -49,16 +49,27 @@ module sha256_stream
output digest_valid_o);
reg first_block;
wire digest_step_valid;
reg first_valid_cycle;
always @(posedge clk) begin
if (s_tvalid_i & s_tready_o)
first_block <= s_tlast_i;
if (s_tvalid_i & s_tready_o) begin
first_block <= s_tlast_i;
first_valid_cycle <= 1;
end
if (digest_valid_o==1) begin
first_valid_cycle <= 0;
end
if (rst) begin
first_block <= 1'b1;
end
first_valid_cycle <= 1'b1;
end
end
assign digest_valid_o = digest_step_valid & first_block & first_valid_cycle;
sha256_core core
(.clk (clk),
.reset_n (~rst),
......@@ -72,6 +83,6 @@ module sha256_stream
.ready(s_tready_o),
.digest (digest_o),
.digest_valid (digest_valid_o));
.digest_valid (digest_step_valid));
endmodule
......@@ -702,80 +702,80 @@ assign axis_mc_udp_tx_data_TDATA = 0;
wire [511:0] ht_dramRdData_data;
wire ht_dramRdData_empty;
(* mark_debug = "true" *) wire ht_dramRdData_empty;
wire ht_dramRdData_almost_empty;
wire ht_dramRdData_read;
(* mark_debug = "true" *) wire ht_dramRdData_read;
wire [63:0] ht_cmd_dramRdData_data;
wire ht_cmd_dramRdData_valid;
wire ht_cmd_dramRdData_stall;
(* mark_debug = "true" *) wire ht_cmd_dramRdData_valid;
(* mark_debug = "true" *) wire ht_cmd_dramRdData_stall;
wire [511:0] ht_dramWrData_data;
wire ht_dramWrData_valid;
wire ht_dramWrData_stall;
(* mark_debug = "true" *) wire ht_dramWrData_valid;
(* mark_debug = "true" *) wire ht_dramWrData_stall;
wire [63:0] ht_cmd_dramWrData_data;
wire ht_cmd_dramWrData_valid;
wire ht_cmd_dramWrData_stall;
(* mark_debug = "true" *) wire ht_cmd_dramWrData_valid;
(* mark_debug = "true" *) wire ht_cmd_dramWrData_stall;
wire [511:0] upd_dramRdData_data;
wire upd_dramRdData_empty;
(* mark_debug = "true" *) wire upd_dramRdData_empty;
wire upd_dramRdData_almost_empty;
wire upd_dramRdData_read;
(* mark_debug = "true" *) wire upd_dramRdData_read;
wire [63:0] upd_cmd_dramRdData_data;
wire upd_cmd_dramRdData_valid;
wire upd_cmd_dramRdData_stall;
(* mark_debug = "true" *) wire upd_cmd_dramRdData_valid;
(* mark_debug = "true" *) wire upd_cmd_dramRdData_stall;
wire [511:0] upd_dramWrData_data;
wire upd_dramWrData_valid;
wire upd_dramWrData_stall;
(* mark_debug = "true" *) wire upd_dramWrData_valid;
(* mark_debug = "true" *) wire upd_dramWrData_stall;
wire [63:0] upd_cmd_dramWrData_data;
wire upd_cmd_dramWrData_valid;
wire upd_cmd_dramWrData_stall;
(* mark_debug = "true" *) wire upd_cmd_dramWrData_valid;
(* mark_debug = "true" *) wire upd_cmd_dramWrData_stall;
wire [63:0] ptr_rdcmd_data;
wire ptr_rdcmd_valid;
wire ptr_rdcmd_ready;
(* mark_debug = "true" *) wire ptr_rdcmd_valid;
(* mark_debug = "true" *) wire ptr_rdcmd_ready;
wire [512-1:0] ptr_rd_data;
wire ptr_rd_valid;
wire ptr_rd_ready;
(* mark_debug = "true" *) wire ptr_rd_valid;
(* mark_debug = "true" *) wire ptr_rd_ready;
wire [512-1:0] ptr_wr_data;
wire ptr_wr_valid;
wire ptr_wr_ready;
(* mark_debug = "true" *) wire ptr_wr_valid;
(* mark_debug = "true" *) wire ptr_wr_ready;
wire [63:0] ptr_wrcmd_data;
wire ptr_wrcmd_valid;
wire ptr_wrcmd_ready;
(* mark_debug = "true" *) wire ptr_wrcmd_valid;
(* mark_debug = "true" *) wire ptr_wrcmd_ready;
wire [63:0] bmap_rdcmd_data;
wire bmap_rdcmd_valid;
wire bmap_rdcmd_ready;
(* mark_debug = "true" *) wire bmap_rdcmd_valid;
(* mark_debug = "true" *) wire bmap_rdcmd_ready;
wire [512-1:0] bmap_rd_data;
wire bmap_rd_valid;
wire bmap_rd_ready;
(* mark_debug = "true" *) wire bmap_rd_valid;
(* mark_debug = "true" *) wire bmap_rd_ready;
wire [512-1:0] bmap_wr_data;
wire bmap_wr_valid;
wire bmap_wr_ready;
(* mark_debug = "true" *) wire bmap_wr_valid;
(* mark_debug = "true" *) wire bmap_wr_ready;
wire [63:0] bmap_wrcmd_data;
wire bmap_wrcmd_valid;
wire bmap_wrcmd_ready;
(* mark_debug = "true" *) wire bmap_wrcmd_valid;
(* mark_debug = "true" *) wire bmap_wrcmd_ready;
assign AXI_M2_Stream_TKEEP = AXI_M2_Stream_TVALID==1 ? 8'b11111111 : 8'b00000000;
......
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