Commit 87eafb5a authored by Zsolt István's avatar Zsolt István
Browse files

collecting files that were changed

parent 3ea992f4
set_property PACKAGE_PIN BB39 [get_ports c0_ddr4_act_n]
set_property PACKAGE_PIN AT36 [get_ports {c0_ddr4_adr[0]}]
set_property PACKAGE_PIN AV36 [get_ports {c0_ddr4_adr[1]}]
set_property PACKAGE_PIN AV37 [get_ports {c0_ddr4_adr[2]}]
set_property PACKAGE_PIN AW35 [get_ports {c0_ddr4_adr[3]}]
set_property PACKAGE_PIN AW36 [get_ports {c0_ddr4_adr[4]}]
set_property PACKAGE_PIN AY36 [get_ports {c0_ddr4_adr[5]}]
set_property PACKAGE_PIN AY35 [get_ports {c0_ddr4_adr[6]}]
set_property PACKAGE_PIN BA40 [get_ports {c0_ddr4_adr[7]}]
set_property PACKAGE_PIN BA37 [get_ports {c0_ddr4_adr[8]}]
set_property PACKAGE_PIN BB37 [get_ports {c0_ddr4_adr[9]}]
set_property PACKAGE_PIN AR35 [get_ports {c0_ddr4_adr[10]}]
set_property PACKAGE_PIN BA39 [get_ports {c0_ddr4_adr[11]}]
set_property PACKAGE_PIN BB40 [get_ports {c0_ddr4_adr[12]}]
set_property PACKAGE_PIN AN36 [get_ports {c0_ddr4_adr[13]}]
set_property PACKAGE_PIN AP35 [get_ports {c0_ddr4_adr[14]}]
set_property PACKAGE_PIN AP36 [get_ports {c0_ddr4_adr[15]}]
set_property PACKAGE_PIN AR36 [get_ports {c0_ddr4_adr[16]}]
set_property PACKAGE_PIN AT35 [get_ports {c0_ddr4_ba[0]}]
set_property PACKAGE_PIN AT34 [get_ports {c0_ddr4_ba[1]}]
set_property PACKAGE_PIN BC37 [get_ports {c0_ddr4_bg[0]}]
set_property PACKAGE_PIN BC39 [get_ports {c0_ddr4_bg[1]}]
set_property PACKAGE_PIN BC38 [get_ports {c0_ddr4_cke[0]}]
set_property PACKAGE_PIN AR33 [get_ports {c0_ddr4_cs_n[0]}]
set_property PACKAGE_PIN AW28 [get_ports {c0_ddr4_dq[0]}]
set_property PACKAGE_PIN AW29 [get_ports {c0_ddr4_dq[1]}]
set_property PACKAGE_PIN BA28 [get_ports {c0_ddr4_dq[2]}]
set_property PACKAGE_PIN BA27 [get_ports {c0_ddr4_dq[3]}]
set_property PACKAGE_PIN BB29 [get_ports {c0_ddr4_dq[4]}]
set_property PACKAGE_PIN BA29 [get_ports {c0_ddr4_dq[5]}]
set_property PACKAGE_PIN BC27 [get_ports {c0_ddr4_dq[6]}]
set_property PACKAGE_PIN BB27 [get_ports {c0_ddr4_dq[7]}]
set_property PACKAGE_PIN BE28 [get_ports {c0_ddr4_dq[8]}]
set_property PACKAGE_PIN BF28 [get_ports {c0_ddr4_dq[9]}]
set_property PACKAGE_PIN BE30 [get_ports {c0_ddr4_dq[10]}]
set_property PACKAGE_PIN BD30 [get_ports {c0_ddr4_dq[11]}]
set_property PACKAGE_PIN BF27 [get_ports {c0_ddr4_dq[12]}]
set_property PACKAGE_PIN BE27 [get_ports {c0_ddr4_dq[13]}]
set_property PACKAGE_PIN BF30 [get_ports {c0_ddr4_dq[14]}]
set_property PACKAGE_PIN BF29 [get_ports {c0_ddr4_dq[15]}]
set_property PACKAGE_PIN BB31 [get_ports {c0_ddr4_dq[16]}]
set_property PACKAGE_PIN BB32 [get_ports {c0_ddr4_dq[17]}]
set_property PACKAGE_PIN AY32 [get_ports {c0_ddr4_dq[18]}]
set_property PACKAGE_PIN AY33 [get_ports {c0_ddr4_dq[19]}]
set_property PACKAGE_PIN BC32 [get_ports {c0_ddr4_dq[20]}]
set_property PACKAGE_PIN BC33 [get_ports {c0_ddr4_dq[21]}]
set_property PACKAGE_PIN BB34 [get_ports {c0_ddr4_dq[22]}]
set_property PACKAGE_PIN BC34 [get_ports {c0_ddr4_dq[23]}]
set_property PACKAGE_PIN AV31 [get_ports {c0_ddr4_dq[24]}]
set_property PACKAGE_PIN AV32 [get_ports {c0_ddr4_dq[25]}]
set_property PACKAGE_PIN AV34 [get_ports {c0_ddr4_dq[26]}]
set_property PACKAGE_PIN AW34 [get_ports {c0_ddr4_dq[27]}]
set_property PACKAGE_PIN AW31 [get_ports {c0_ddr4_dq[28]}]
set_property PACKAGE_PIN AY31 [get_ports {c0_ddr4_dq[29]}]
set_property PACKAGE_PIN BA35 [get_ports {c0_ddr4_dq[30]}]
set_property PACKAGE_PIN BA34 [get_ports {c0_ddr4_dq[31]}]
set_property PACKAGE_PIN AL30 [get_ports {c0_ddr4_dq[32]}]
set_property PACKAGE_PIN AM30 [get_ports {c0_ddr4_dq[33]}]
set_property PACKAGE_PIN AU32 [get_ports {c0_ddr4_dq[34]}]
set_property PACKAGE_PIN AT32 [get_ports {c0_ddr4_dq[35]}]
set_property PACKAGE_PIN AN31 [get_ports {c0_ddr4_dq[36]}]
set_property PACKAGE_PIN AN32 [get_ports {c0_ddr4_dq[37]}]
set_property PACKAGE_PIN AR32 [get_ports {c0_ddr4_dq[38]}]
set_property PACKAGE_PIN AR31 [get_ports {c0_ddr4_dq[39]}]
set_property PACKAGE_PIN AP29 [get_ports {c0_ddr4_dq[40]}]
set_property PACKAGE_PIN AP28 [get_ports {c0_ddr4_dq[41]}]
set_property PACKAGE_PIN AN27 [get_ports {c0_ddr4_dq[42]}]
set_property PACKAGE_PIN AM27 [get_ports {c0_ddr4_dq[43]}]
set_property PACKAGE_PIN AN29 [get_ports {c0_ddr4_dq[44]}]
set_property PACKAGE_PIN AM29 [get_ports {c0_ddr4_dq[45]}]
set_property PACKAGE_PIN AR27 [get_ports {c0_ddr4_dq[46]}]
set_property PACKAGE_PIN AR28 [get_ports {c0_ddr4_dq[47]}]
set_property PACKAGE_PIN AT28 [get_ports {c0_ddr4_dq[48]}]
set_property PACKAGE_PIN AV27 [get_ports {c0_ddr4_dq[49]}]
set_property PACKAGE_PIN AU27 [get_ports {c0_ddr4_dq[50]}]
set_property PACKAGE_PIN AT27 [get_ports {c0_ddr4_dq[51]}]
set_property PACKAGE_PIN AV29 [get_ports {c0_ddr4_dq[52]}]
set_property PACKAGE_PIN AY30 [get_ports {c0_ddr4_dq[53]}]
set_property PACKAGE_PIN AW30 [get_ports {c0_ddr4_dq[54]}]
set_property PACKAGE_PIN AV28 [get_ports {c0_ddr4_dq[55]}]
set_property PACKAGE_PIN BD34 [get_ports {c0_ddr4_dq[56]}]
set_property PACKAGE_PIN BD33 [get_ports {c0_ddr4_dq[57]}]
set_property PACKAGE_PIN BE33 [get_ports {c0_ddr4_dq[58]}]
set_property PACKAGE_PIN BD35 [get_ports {c0_ddr4_dq[59]}]
set_property PACKAGE_PIN BF32 [get_ports {c0_ddr4_dq[60]}]
set_property PACKAGE_PIN BF33 [get_ports {c0_ddr4_dq[61]}]
set_property PACKAGE_PIN BF34 [get_ports {c0_ddr4_dq[62]}]
set_property PACKAGE_PIN BF35 [get_ports {c0_ddr4_dq[63]}]
set_property PACKAGE_PIN BD40 [get_ports {c0_ddr4_dq[64]}]
set_property PACKAGE_PIN BD39 [get_ports {c0_ddr4_dq[65]}]
set_property PACKAGE_PIN BF43 [get_ports {c0_ddr4_dq[66]}]
set_property PACKAGE_PIN BF42 [get_ports {c0_ddr4_dq[67]}]
set_property PACKAGE_PIN BF37 [get_ports {c0_ddr4_dq[68]}]
set_property PACKAGE_PIN BE37 [get_ports {c0_ddr4_dq[69]}]
set_property PACKAGE_PIN BE40 [get_ports {c0_ddr4_dq[70]}]
set_property PACKAGE_PIN BF41 [get_ports {c0_ddr4_dq[71]}]
set_property PACKAGE_PIN AP34 [get_ports {c0_ddr4_odt[0]}]
set_property PACKAGE_PIN AU31 [get_ports c0_ddr4_reset_n]
set_property PACKAGE_PIN AU36 [get_ports c0_ddr4_parity]
set_property PACKAGE_PIN AY37 [get_ports c0_sys_clk_p]
set_property PACKAGE_PIN AY38 [get_ports c0_sys_clk_n]
set_property PACKAGE_PIN BA30 [get_ports {c0_ddr4_dqs_t[0]}]
set_property PACKAGE_PIN BB30 [get_ports {c0_ddr4_dqs_c[0]}]
set_property PACKAGE_PIN AM31 [get_ports {c0_ddr4_dqs_t[8]}]
set_property PACKAGE_PIN AM32 [get_ports {c0_ddr4_dqs_c[8]}]
set_property PACKAGE_PIN BE38 [get_ports {c0_ddr4_dqs_t[16]}]
set_property PACKAGE_PIN BF38 [get_ports {c0_ddr4_dqs_c[16]}]
set_property PACKAGE_PIN AP30 [get_ports {c0_ddr4_dqs_t[9]}]
set_property PACKAGE_PIN AP31 [get_ports {c0_ddr4_dqs_c[9]}]
set_property PACKAGE_PIN BB26 [get_ports {c0_ddr4_dqs_t[1]}]
set_property PACKAGE_PIN BC26 [get_ports {c0_ddr4_dqs_c[1]}]
set_property PACKAGE_PIN BF39 [get_ports {c0_ddr4_dqs_t[17]}]
set_property PACKAGE_PIN BF40 [get_ports {c0_ddr4_dqs_c[17]}]
set_property PACKAGE_PIN BE35 [get_ports {c0_ddr4_dqs_t[14]}]
set_property PACKAGE_PIN BE36 [get_ports {c0_ddr4_dqs_c[14]}]
set_property PACKAGE_PIN AV33 [get_ports {c0_ddr4_dqs_t[6]}]
set_property PACKAGE_PIN AW33 [get_ports {c0_ddr4_dqs_c[6]}]
set_property PACKAGE_PIN BE31 [get_ports {c0_ddr4_dqs_t[15]}]
set_property PACKAGE_PIN BE32 [get_ports {c0_ddr4_dqs_c[15]}]
set_property PACKAGE_PIN BA32 [get_ports {c0_ddr4_dqs_t[7]}]
set_property PACKAGE_PIN BA33 [get_ports {c0_ddr4_dqs_c[7]}]
set_property PACKAGE_PIN AU29 [get_ports {c0_ddr4_dqs_t[12]}]
set_property PACKAGE_PIN AU30 [get_ports {c0_ddr4_dqs_c[12]}]
set_property PACKAGE_PIN BB35 [get_ports {c0_ddr4_dqs_t[4]}]
set_property PACKAGE_PIN BB36 [get_ports {c0_ddr4_dqs_c[4]}]
set_property PACKAGE_PIN AY27 [get_ports {c0_ddr4_dqs_t[13]}]
set_property PACKAGE_PIN AY28 [get_ports {c0_ddr4_dqs_c[13]}]
set_property PACKAGE_PIN AV38 [get_ports {c0_ddr4_ck_t[0]}]
set_property PACKAGE_PIN AW38 [get_ports {c0_ddr4_ck_c[0]}]
set_property PACKAGE_PIN BC31 [get_ports {c0_ddr4_dqs_t[5]}]
set_property PACKAGE_PIN BD31 [get_ports {c0_ddr4_dqs_c[5]}]
set_property PACKAGE_PIN BD26 [get_ports {c0_ddr4_dqs_t[3]}]
set_property PACKAGE_PIN BE26 [get_ports {c0_ddr4_dqs_c[3]}]
set_property PACKAGE_PIN BD28 [get_ports {c0_ddr4_dqs_t[2]}]
set_property PACKAGE_PIN BD29 [get_ports {c0_ddr4_dqs_c[2]}]
set_property PACKAGE_PIN AL28 [get_ports {c0_ddr4_dqs_t[10]}]
set_property PACKAGE_PIN AL29 [get_ports {c0_ddr4_dqs_c[10]}]
set_property PACKAGE_PIN AR30 [get_ports {c0_ddr4_dqs_t[11]}]
set_property PACKAGE_PIN AT30 [get_ports {c0_ddr4_dqs_c[11]}]
set_property PACKAGE_PIN AW25 [get_ports c1_ddr4_act_n]
set_property PACKAGE_PIN AN24 [get_ports {c1_ddr4_adr[0]}]
set_property PACKAGE_PIN AT24 [get_ports {c1_ddr4_adr[1]}]
set_property PACKAGE_PIN AW24 [get_ports {c1_ddr4_adr[2]}]
set_property PACKAGE_PIN AN26 [get_ports {c1_ddr4_adr[3]}]
set_property PACKAGE_PIN AY22 [get_ports {c1_ddr4_adr[4]}]
set_property PACKAGE_PIN AY23 [get_ports {c1_ddr4_adr[5]}]
set_property PACKAGE_PIN AV24 [get_ports {c1_ddr4_adr[6]}]
set_property PACKAGE_PIN BA22 [get_ports {c1_ddr4_adr[7]}]
set_property PACKAGE_PIN AY25 [get_ports {c1_ddr4_adr[8]}]
set_property PACKAGE_PIN BA23 [get_ports {c1_ddr4_adr[9]}]
set_property PACKAGE_PIN AM26 [get_ports {c1_ddr4_adr[10]}]
set_property PACKAGE_PIN BA25 [get_ports {c1_ddr4_adr[11]}]
set_property PACKAGE_PIN BB22 [get_ports {c1_ddr4_adr[12]}]
set_property PACKAGE_PIN AL24 [get_ports {c1_ddr4_adr[13]}]
set_property PACKAGE_PIN AL25 [get_ports {c1_ddr4_adr[14]}]
set_property PACKAGE_PIN AM25 [get_ports {c1_ddr4_adr[15]}]
set_property PACKAGE_PIN AN23 [get_ports {c1_ddr4_adr[16]}]
set_property PACKAGE_PIN AU24 [get_ports {c1_ddr4_ba[0]}]
set_property PACKAGE_PIN AP26 [get_ports {c1_ddr4_ba[1]}]
set_property PACKAGE_PIN BC22 [get_ports {c1_ddr4_bg[0]}]
set_property PACKAGE_PIN AW26 [get_ports {c1_ddr4_bg[1]}]
set_property PACKAGE_PIN BB25 [get_ports {c1_ddr4_cke[0]}]
set_property PACKAGE_PIN AV23 [get_ports {c1_ddr4_cs_n[0]}]
set_property PACKAGE_PIN BD9 [get_ports {c1_ddr4_dq[0]}]
set_property PACKAGE_PIN BD7 [get_ports {c1_ddr4_dq[1]}]
set_property PACKAGE_PIN BC7 [get_ports {c1_ddr4_dq[2]}]
set_property PACKAGE_PIN BD8 [get_ports {c1_ddr4_dq[3]}]
set_property PACKAGE_PIN BD10 [get_ports {c1_ddr4_dq[4]}]
set_property PACKAGE_PIN BE10 [get_ports {c1_ddr4_dq[5]}]
set_property PACKAGE_PIN BE7 [get_ports {c1_ddr4_dq[6]}]
set_property PACKAGE_PIN BF7 [get_ports {c1_ddr4_dq[7]}]
set_property PACKAGE_PIN AU13 [get_ports {c1_ddr4_dq[8]}]
set_property PACKAGE_PIN AV13 [get_ports {c1_ddr4_dq[9]}]
set_property PACKAGE_PIN AW13 [get_ports {c1_ddr4_dq[10]}]
set_property PACKAGE_PIN AW14 [get_ports {c1_ddr4_dq[11]}]
set_property PACKAGE_PIN AU14 [get_ports {c1_ddr4_dq[12]}]
set_property PACKAGE_PIN AY11 [get_ports {c1_ddr4_dq[13]}]
set_property PACKAGE_PIN AV14 [get_ports {c1_ddr4_dq[14]}]
set_property PACKAGE_PIN BA11 [get_ports {c1_ddr4_dq[15]}]
set_property PACKAGE_PIN BA12 [get_ports {c1_ddr4_dq[16]}]
set_property PACKAGE_PIN BB12 [get_ports {c1_ddr4_dq[17]}]
set_property PACKAGE_PIN BA13 [get_ports {c1_ddr4_dq[18]}]
set_property PACKAGE_PIN BA14 [get_ports {c1_ddr4_dq[19]}]
set_property PACKAGE_PIN BC9 [get_ports {c1_ddr4_dq[20]}]
set_property PACKAGE_PIN BB9 [get_ports {c1_ddr4_dq[21]}]
set_property PACKAGE_PIN BA7 [get_ports {c1_ddr4_dq[22]}]
set_property PACKAGE_PIN BA8 [get_ports {c1_ddr4_dq[23]}]
set_property PACKAGE_PIN AN13 [get_ports {c1_ddr4_dq[24]}]
set_property PACKAGE_PIN AR13 [get_ports {c1_ddr4_dq[25]}]
set_property PACKAGE_PIN AM13 [get_ports {c1_ddr4_dq[26]}]
set_property PACKAGE_PIN AP13 [get_ports {c1_ddr4_dq[27]}]
set_property PACKAGE_PIN AM14 [get_ports {c1_ddr4_dq[28]}]
set_property PACKAGE_PIN AR15 [get_ports {c1_ddr4_dq[29]}]
set_property PACKAGE_PIN AL14 [get_ports {c1_ddr4_dq[30]}]
set_property PACKAGE_PIN AT15 [get_ports {c1_ddr4_dq[31]}]
set_property PACKAGE_PIN BE13 [get_ports {c1_ddr4_dq[32]}]
set_property PACKAGE_PIN BD14 [get_ports {c1_ddr4_dq[33]}]
set_property PACKAGE_PIN BF12 [get_ports {c1_ddr4_dq[34]}]
set_property PACKAGE_PIN BD13 [get_ports {c1_ddr4_dq[35]}]
set_property PACKAGE_PIN BD15 [get_ports {c1_ddr4_dq[36]}]
set_property PACKAGE_PIN BD16 [get_ports {c1_ddr4_dq[37]}]
set_property PACKAGE_PIN BF14 [get_ports {c1_ddr4_dq[38]}]
set_property PACKAGE_PIN BF13 [get_ports {c1_ddr4_dq[39]}]
set_property PACKAGE_PIN AY17 [get_ports {c1_ddr4_dq[40]}]
set_property PACKAGE_PIN BA17 [get_ports {c1_ddr4_dq[41]}]
set_property PACKAGE_PIN AY18 [get_ports {c1_ddr4_dq[42]}]
set_property PACKAGE_PIN BA18 [get_ports {c1_ddr4_dq[43]}]
set_property PACKAGE_PIN BA15 [get_ports {c1_ddr4_dq[44]}]
set_property PACKAGE_PIN BB15 [get_ports {c1_ddr4_dq[45]}]
set_property PACKAGE_PIN BC11 [get_ports {c1_ddr4_dq[46]}]
set_property PACKAGE_PIN BD11 [get_ports {c1_ddr4_dq[47]}]
set_property PACKAGE_PIN AV16 [get_ports {c1_ddr4_dq[48]}]
set_property PACKAGE_PIN AV17 [get_ports {c1_ddr4_dq[49]}]
set_property PACKAGE_PIN AU16 [get_ports {c1_ddr4_dq[50]}]
set_property PACKAGE_PIN AU17 [get_ports {c1_ddr4_dq[51]}]
set_property PACKAGE_PIN BB17 [get_ports {c1_ddr4_dq[52]}]
set_property PACKAGE_PIN BB16 [get_ports {c1_ddr4_dq[53]}]
set_property PACKAGE_PIN AT18 [get_ports {c1_ddr4_dq[54]}]
set_property PACKAGE_PIN AT17 [get_ports {c1_ddr4_dq[55]}]
set_property PACKAGE_PIN AM15 [get_ports {c1_ddr4_dq[56]}]
set_property PACKAGE_PIN AL15 [get_ports {c1_ddr4_dq[57]}]
set_property PACKAGE_PIN AN17 [get_ports {c1_ddr4_dq[58]}]
set_property PACKAGE_PIN AN16 [get_ports {c1_ddr4_dq[59]}]
set_property PACKAGE_PIN AR18 [get_ports {c1_ddr4_dq[60]}]
set_property PACKAGE_PIN AP18 [get_ports {c1_ddr4_dq[61]}]
set_property PACKAGE_PIN AL17 [get_ports {c1_ddr4_dq[62]}]
set_property PACKAGE_PIN AL16 [get_ports {c1_ddr4_dq[63]}]
set_property PACKAGE_PIN BF25 [get_ports {c1_ddr4_dq[64]}]
set_property PACKAGE_PIN BF24 [get_ports {c1_ddr4_dq[65]}]
set_property PACKAGE_PIN BD25 [get_ports {c1_ddr4_dq[66]}]
set_property PACKAGE_PIN BE25 [get_ports {c1_ddr4_dq[67]}]
set_property PACKAGE_PIN BD23 [get_ports {c1_ddr4_dq[68]}]
set_property PACKAGE_PIN BC23 [get_ports {c1_ddr4_dq[69]}]
set_property PACKAGE_PIN BF23 [get_ports {c1_ddr4_dq[70]}]
set_property PACKAGE_PIN BE23 [get_ports {c1_ddr4_dq[71]}]
set_property PACKAGE_PIN AW23 [get_ports {c1_ddr4_odt[0]}]
set_property PACKAGE_PIN AR17 [get_ports c1_ddr4_reset_n]
set_property PACKAGE_PIN AT23 [get_ports c1_ddr4_parity]
set_property PACKAGE_PIN AW20 [get_ports c1_sys_clk_p]
set_property PACKAGE_PIN AW19 [get_ports c1_sys_clk_n]
set_property PACKAGE_PIN BF10 [get_ports {c1_ddr4_dqs_t[0]}]
set_property PACKAGE_PIN BF9 [get_ports {c1_ddr4_dqs_c[0]}]
set_property PACKAGE_PIN BE12 [get_ports {c1_ddr4_dqs_t[8]}]
set_property PACKAGE_PIN BE11 [get_ports {c1_ddr4_dqs_c[8]}]
set_property PACKAGE_PIN BC24 [get_ports {c1_ddr4_dqs_t[16]}]
set_property PACKAGE_PIN BD24 [get_ports {c1_ddr4_dqs_c[16]}]
set_property PACKAGE_PIN BE15 [get_ports {c1_ddr4_dqs_t[9]}]
set_property PACKAGE_PIN BF15 [get_ports {c1_ddr4_dqs_c[9]}]
set_property PACKAGE_PIN BE8 [get_ports {c1_ddr4_dqs_t[1]}]
set_property PACKAGE_PIN BF8 [get_ports {c1_ddr4_dqs_c[1]}]
set_property PACKAGE_PIN BE22 [get_ports {c1_ddr4_dqs_t[17]}]
set_property PACKAGE_PIN BF22 [get_ports {c1_ddr4_dqs_c[17]}]
set_property PACKAGE_PIN AP16 [get_ports {c1_ddr4_dqs_t[14]}]
set_property PACKAGE_PIN AR16 [get_ports {c1_ddr4_dqs_c[14]}]
set_property PACKAGE_PIN AT14 [get_ports {c1_ddr4_dqs_t[6]}]
set_property PACKAGE_PIN AT13 [get_ports {c1_ddr4_dqs_c[6]}]
set_property PACKAGE_PIN AM17 [get_ports {c1_ddr4_dqs_t[15]}]
set_property PACKAGE_PIN AM16 [get_ports {c1_ddr4_dqs_c[15]}]
set_property PACKAGE_PIN AN14 [get_ports {c1_ddr4_dqs_t[7]}]
set_property PACKAGE_PIN AP14 [get_ports {c1_ddr4_dqs_c[7]}]
set_property PACKAGE_PIN AV18 [get_ports {c1_ddr4_dqs_t[12]}]
set_property PACKAGE_PIN AW18 [get_ports {c1_ddr4_dqs_c[12]}]
set_property PACKAGE_PIN BB11 [get_ports {c1_ddr4_dqs_t[4]}]
set_property PACKAGE_PIN BB10 [get_ports {c1_ddr4_dqs_c[4]}]
set_property PACKAGE_PIN AW16 [get_ports {c1_ddr4_dqs_t[13]}]
set_property PACKAGE_PIN AY16 [get_ports {c1_ddr4_dqs_c[13]}]
set_property PACKAGE_PIN AT25 [get_ports {c1_ddr4_ck_t[0]}]
set_property PACKAGE_PIN AU25 [get_ports {c1_ddr4_ck_c[0]}]
set_property PACKAGE_PIN BA10 [get_ports {c1_ddr4_dqs_t[5]}]
set_property PACKAGE_PIN BA9 [get_ports {c1_ddr4_dqs_c[5]}]
set_property PACKAGE_PIN AY13 [get_ports {c1_ddr4_dqs_t[3]}]
set_property PACKAGE_PIN AY12 [get_ports {c1_ddr4_dqs_c[3]}]
set_property PACKAGE_PIN AW15 [get_ports {c1_ddr4_dqs_t[2]}]
set_property PACKAGE_PIN AY15 [get_ports {c1_ddr4_dqs_c[2]}]
set_property PACKAGE_PIN BC13 [get_ports {c1_ddr4_dqs_t[10]}]
set_property PACKAGE_PIN BC12 [get_ports {c1_ddr4_dqs_c[10]}]
set_property PACKAGE_PIN BB14 [get_ports {c1_ddr4_dqs_t[11]}]
set_property PACKAGE_PIN BC14 [get_ports {c1_ddr4_dqs_c[11]}]
set_property PACKAGE_PIN N4 [get_ports {gt_rxp_in[0]}]
set_property PACKAGE_PIN N3 [get_ports {gt_rxn_in[0]}]
set_property PACKAGE_PIN N9 [get_ports {gt_txp_out[0]}]
set_property PACKAGE_PIN N8 [get_ports {gt_txn_out[0]}]
set_property PACKAGE_PIN M10 [get_ports gt_refclk_n]
set_property PACKAGE_PIN M11 [get_ports gt_refclk_p]
set_property PACKAGE_PIN J16 [get_ports c300_p]
set_property PACKAGE_PIN H16 [get_ports c300_n]
set_property IOSTANDARD LVDS [get_ports c300_p]
set_property IOSTANDARD LVDS [get_ports c300_n]
#create_clock -period 6.400 -name uclk [get_pins clockdown/inst/clk_out1]
#set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] 6.400
#set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] 6.400
#set_max_delay -datapath_only -from [get_clocks uclk] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] 8.000
#set_max_delay -datapath_only -from [get_clocks uclk] -to [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] 8.000
#set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks uclk] 6.400
#set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ */channel_inst/*_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks uclk] 6.400
##### XXXX
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list network_module_inst/ethernet_inst/inst/i_core_gtwiz_userclk_tx_inst_0/tx_clk_out_0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 8 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {multiuser_kvs_top/muukvs_instance/malloc_error_state[0]} {multiuser_kvs_top/muukvs_instance/malloc_error_state[1]} {multiuser_kvs_top/muukvs_instance/malloc_error_state[2]} {multiuser_kvs_top/muukvs_instance/malloc_error_state[3]} {multiuser_kvs_top/muukvs_instance/malloc_error_state[4]} {multiuser_kvs_top/muukvs_instance/malloc_error_state[5]} {multiuser_kvs_top/muukvs_instance/malloc_error_state[6]} {multiuser_kvs_top/muukvs_instance/malloc_error_state[7]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 64 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {upd_cmd_dramWrData_data[0]} {upd_cmd_dramWrData_data[1]} {upd_cmd_dramWrData_data[2]} {upd_cmd_dramWrData_data[3]} {upd_cmd_dramWrData_data[4]} {upd_cmd_dramWrData_data[5]} {upd_cmd_dramWrData_data[6]} {upd_cmd_dramWrData_data[7]} {upd_cmd_dramWrData_data[8]} {upd_cmd_dramWrData_data[9]} {upd_cmd_dramWrData_data[10]} {upd_cmd_dramWrData_data[11]} {upd_cmd_dramWrData_data[12]} {upd_cmd_dramWrData_data[13]} {upd_cmd_dramWrData_data[14]} {upd_cmd_dramWrData_data[15]} {upd_cmd_dramWrData_data[16]} {upd_cmd_dramWrData_data[17]} {upd_cmd_dramWrData_data[18]} {upd_cmd_dramWrData_data[19]} {upd_cmd_dramWrData_data[20]} {upd_cmd_dramWrData_data[21]} {upd_cmd_dramWrData_data[22]} {upd_cmd_dramWrData_data[23]} {upd_cmd_dramWrData_data[24]} {upd_cmd_dramWrData_data[25]} {upd_cmd_dramWrData_data[26]} {upd_cmd_dramWrData_data[27]} {upd_cmd_dramWrData_data[28]} {upd_cmd_dramWrData_data[29]} {upd_cmd_dramWrData_data[30]} {upd_cmd_dramWrData_data[31]} {upd_cmd_dramWrData_data[32]} {upd_cmd_dramWrData_data[33]} {upd_cmd_dramWrData_data[34]} {upd_cmd_dramWrData_data[35]} {upd_cmd_dramWrData_data[36]} {upd_cmd_dramWrData_data[37]} {upd_cmd_dramWrData_data[38]} {upd_cmd_dramWrData_data[39]} {upd_cmd_dramWrData_data[40]} {upd_cmd_dramWrData_data[41]} {upd_cmd_dramWrData_data[42]} {upd_cmd_dramWrData_data[43]} {upd_cmd_dramWrData_data[44]} {upd_cmd_dramWrData_data[45]} {upd_cmd_dramWrData_data[46]} {upd_cmd_dramWrData_data[47]} {upd_cmd_dramWrData_data[48]} {upd_cmd_dramWrData_data[49]} {upd_cmd_dramWrData_data[50]} {upd_cmd_dramWrData_data[51]} {upd_cmd_dramWrData_data[52]} {upd_cmd_dramWrData_data[53]} {upd_cmd_dramWrData_data[54]} {upd_cmd_dramWrData_data[55]} {upd_cmd_dramWrData_data[56]} {upd_cmd_dramWrData_data[57]} {upd_cmd_dramWrData_data[58]} {upd_cmd_dramWrData_data[59]} {upd_cmd_dramWrData_data[60]} {upd_cmd_dramWrData_data[61]} {upd_cmd_dramWrData_data[62]} {upd_cmd_dramWrData_data[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 64 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {ht_cmd_dramRdData_data[0]} {ht_cmd_dramRdData_data[1]} {ht_cmd_dramRdData_data[2]} {ht_cmd_dramRdData_data[3]} {ht_cmd_dramRdData_data[4]} {ht_cmd_dramRdData_data[5]} {ht_cmd_dramRdData_data[6]} {ht_cmd_dramRdData_data[7]} {ht_cmd_dramRdData_data[8]} {ht_cmd_dramRdData_data[9]} {ht_cmd_dramRdData_data[10]} {ht_cmd_dramRdData_data[11]} {ht_cmd_dramRdData_data[12]} {ht_cmd_dramRdData_data[13]} {ht_cmd_dramRdData_data[14]} {ht_cmd_dramRdData_data[15]} {ht_cmd_dramRdData_data[16]} {ht_cmd_dramRdData_data[17]} {ht_cmd_dramRdData_data[18]} {ht_cmd_dramRdData_data[19]} {ht_cmd_dramRdData_data[20]} {ht_cmd_dramRdData_data[21]} {ht_cmd_dramRdData_data[22]} {ht_cmd_dramRdData_data[23]} {ht_cmd_dramRdData_data[24]} {ht_cmd_dramRdData_data[25]} {ht_cmd_dramRdData_data[26]} {ht_cmd_dramRdData_data[27]} {ht_cmd_dramRdData_data[28]} {ht_cmd_dramRdData_data[29]} {ht_cmd_dramRdData_data[30]} {ht_cmd_dramRdData_data[31]} {ht_cmd_dramRdData_data[32]} {ht_cmd_dramRdData_data[33]} {ht_cmd_dramRdData_data[34]} {ht_cmd_dramRdData_data[35]} {ht_cmd_dramRdData_data[36]} {ht_cmd_dramRdData_data[37]} {ht_cmd_dramRdData_data[38]} {ht_cmd_dramRdData_data[39]} {ht_cmd_dramRdData_data[40]} {ht_cmd_dramRdData_data[41]} {ht_cmd_dramRdData_data[42]} {ht_cmd_dramRdData_data[43]} {ht_cmd_dramRdData_data[44]} {ht_cmd_dramRdData_data[45]} {ht_cmd_dramRdData_data[46]} {ht_cmd_dramRdData_data[47]} {ht_cmd_dramRdData_data[48]} {ht_cmd_dramRdData_data[49]} {ht_cmd_dramRdData_data[50]} {ht_cmd_dramRdData_data[51]} {ht_cmd_dramRdData_data[52]} {ht_cmd_dramRdData_data[53]} {ht_cmd_dramRdData_data[54]} {ht_cmd_dramRdData_data[55]} {ht_cmd_dramRdData_data[56]} {ht_cmd_dramRdData_data[57]} {ht_cmd_dramRdData_data[58]} {ht_cmd_dramRdData_data[59]} {ht_cmd_dramRdData_data[60]} {ht_cmd_dramRdData_data[61]} {ht_cmd_dramRdData_data[62]} {ht_cmd_dramRdData_data[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 64 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {ht_cmd_dramWrData_data[0]} {ht_cmd_dramWrData_data[1]} {ht_cmd_dramWrData_data[2]} {ht_cmd_dramWrData_data[3]} {ht_cmd_dramWrData_data[4]} {ht_cmd_dramWrData_data[5]} {ht_cmd_dramWrData_data[6]} {ht_cmd_dramWrData_data[7]} {ht_cmd_dramWrData_data[8]} {ht_cmd_dramWrData_data[9]} {ht_cmd_dramWrData_data[10]} {ht_cmd_dramWrData_data[11]} {ht_cmd_dramWrData_data[12]} {ht_cmd_dramWrData_data[13]} {ht_cmd_dramWrData_data[14]} {ht_cmd_dramWrData_data[15]} {ht_cmd_dramWrData_data[16]} {ht_cmd_dramWrData_data[17]} {ht_cmd_dramWrData_data[18]} {ht_cmd_dramWrData_data[19]} {ht_cmd_dramWrData_data[20]} {ht_cmd_dramWrData_data[21]} {ht_cmd_dramWrData_data[22]} {ht_cmd_dramWrData_data[23]} {ht_cmd_dramWrData_data[24]} {ht_cmd_dramWrData_data[25]} {ht_cmd_dramWrData_data[26]} {ht_cmd_dramWrData_data[27]} {ht_cmd_dramWrData_data[28]} {ht_cmd_dramWrData_data[29]} {ht_cmd_dramWrData_data[30]} {ht_cmd_dramWrData_data[31]} {ht_cmd_dramWrData_data[32]} {ht_cmd_dramWrData_data[33]} {ht_cmd_dramWrData_data[34]} {ht_cmd_dramWrData_data[35]} {ht_cmd_dramWrData_data[36]} {ht_cmd_dramWrData_data[37]} {ht_cmd_dramWrData_data[38]} {ht_cmd_dramWrData_data[39]} {ht_cmd_dramWrData_data[40]} {ht_cmd_dramWrData_data[41]} {ht_cmd_dramWrData_data[42]} {ht_cmd_dramWrData_data[43]} {ht_cmd_dramWrData_data[44]} {ht_cmd_dramWrData_data[45]} {ht_cmd_dramWrData_data[46]} {ht_cmd_dramWrData_data[47]} {ht_cmd_dramWrData_data[48]} {ht_cmd_dramWrData_data[49]} {ht_cmd_dramWrData_data[50]} {ht_cmd_dramWrData_data[51]} {ht_cmd_dramWrData_data[52]} {ht_cmd_dramWrData_data[53]} {ht_cmd_dramWrData_data[54]} {ht_cmd_dramWrData_data[55]} {ht_cmd_dramWrData_data[56]} {ht_cmd_dramWrData_data[57]} {ht_cmd_dramWrData_data[58]} {ht_cmd_dramWrData_data[59]} {ht_cmd_dramWrData_data[60]} {ht_cmd_dramWrData_data[61]} {ht_cmd_dramWrData_data[62]} {ht_cmd_dramWrData_data[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 64 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {upd_cmd_dramRdData_data[0]} {upd_cmd_dramRdData_data[1]} {upd_cmd_dramRdData_data[2]} {upd_cmd_dramRdData_data[3]} {upd_cmd_dramRdData_data[4]} {upd_cmd_dramRdData_data[5]} {upd_cmd_dramRdData_data[6]} {upd_cmd_dramRdData_data[7]} {upd_cmd_dramRdData_data[8]} {upd_cmd_dramRdData_data[9]} {upd_cmd_dramRdData_data[10]} {upd_cmd_dramRdData_data[11]} {upd_cmd_dramRdData_data[12]} {upd_cmd_dramRdData_data[13]} {upd_cmd_dramRdData_data[14]} {upd_cmd_dramRdData_data[15]} {upd_cmd_dramRdData_data[16]} {upd_cmd_dramRdData_data[17]} {upd_cmd_dramRdData_data[18]} {upd_cmd_dramRdData_data[19]} {upd_cmd_dramRdData_data[20]} {upd_cmd_dramRdData_data[21]} {upd_cmd_dramRdData_data[22]} {upd_cmd_dramRdData_data[23]} {upd_cmd_dramRdData_data[24]} {upd_cmd_dramRdData_data[25]} {upd_cmd_dramRdData_data[26]} {upd_cmd_dramRdData_data[27]} {upd_cmd_dramRdData_data[28]} {upd_cmd_dramRdData_data[29]} {upd_cmd_dramRdData_data[30]} {upd_cmd_dramRdData_data[31]} {upd_cmd_dramRdData_data[32]} {upd_cmd_dramRdData_data[33]} {upd_cmd_dramRdData_data[34]} {upd_cmd_dramRdData_data[35]} {upd_cmd_dramRdData_data[36]} {upd_cmd_dramRdData_data[37]} {upd_cmd_dramRdData_data[38]} {upd_cmd_dramRdData_data[39]} {upd_cmd_dramRdData_data[40]} {upd_cmd_dramRdData_data[41]} {upd_cmd_dramRdData_data[42]} {upd_cmd_dramRdData_data[43]} {upd_cmd_dramRdData_data[44]} {upd_cmd_dramRdData_data[45]} {upd_cmd_dramRdData_data[46]} {upd_cmd_dramRdData_data[47]} {upd_cmd_dramRdData_data[48]} {upd_cmd_dramRdData_data[49]} {upd_cmd_dramRdData_data[50]} {upd_cmd_dramRdData_data[51]} {upd_cmd_dramRdData_data[52]} {upd_cmd_dramRdData_data[53]} {upd_cmd_dramRdData_data[54]} {upd_cmd_dramRdData_data[55]} {upd_cmd_dramRdData_data[56]} {upd_cmd_dramRdData_data[57]} {upd_cmd_dramRdData_data[58]} {upd_cmd_dramRdData_data[59]} {upd_cmd_dramRdData_data[60]} {upd_cmd_dramRdData_data[61]} {upd_cmd_dramRdData_data[62]} {upd_cmd_dramRdData_data[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {axis_tx_data_TDATA[0]} {axis_tx_data_TDATA[1]} {axis_tx_data_TDATA[2]} {axis_tx_data_TDATA[3]} {axis_tx_data_TDATA[4]} {axis_tx_data_TDATA[5]} {axis_tx_data_TDATA[6]} {axis_tx_data_TDATA[7]} {axis_tx_data_TDATA[8]} {axis_tx_data_TDATA[9]} {axis_tx_data_TDATA[10]} {axis_tx_data_TDATA[11]} {axis_tx_data_TDATA[12]} {axis_tx_data_TDATA[13]} {axis_tx_data_TDATA[14]} {axis_tx_data_TDATA[15]} {axis_tx_data_TDATA[16]} {axis_tx_data_TDATA[17]} {axis_tx_data_TDATA[18]} {axis_tx_data_TDATA[19]} {axis_tx_data_TDATA[20]} {axis_tx_data_TDATA[21]} {axis_tx_data_TDATA[22]} {axis_tx_data_TDATA[23]} {axis_tx_data_TDATA[24]} {axis_tx_data_TDATA[25]} {axis_tx_data_TDATA[26]} {axis_tx_data_TDATA[27]} {axis_tx_data_TDATA[28]} {axis_tx_data_TDATA[29]} {axis_tx_data_TDATA[30]} {axis_tx_data_TDATA[31]} {axis_tx_data_TDATA[32]} {axis_tx_data_TDATA[33]} {axis_tx_data_TDATA[34]} {axis_tx_data_TDATA[35]} {axis_tx_data_TDATA[36]} {axis_tx_data_TDATA[37]} {axis_tx_data_TDATA[38]} {axis_tx_data_TDATA[39]} {axis_tx_data_TDATA[40]} {axis_tx_data_TDATA[41]} {axis_tx_data_TDATA[42]} {axis_tx_data_TDATA[43]} {axis_tx_data_TDATA[44]} {axis_tx_data_TDATA[45]} {axis_tx_data_TDATA[46]} {axis_tx_data_TDATA[47]} {axis_tx_data_TDATA[48]} {axis_tx_data_TDATA[49]} {axis_tx_data_TDATA[50]} {axis_tx_data_TDATA[51]} {axis_tx_data_TDATA[52]} {axis_tx_data_TDATA[53]} {axis_tx_data_TDATA[54]} {axis_tx_data_TDATA[55]} {axis_tx_data_TDATA[56]} {axis_tx_data_TDATA[57]} {axis_tx_data_TDATA[58]} {axis_tx_data_TDATA[59]} {axis_tx_data_TDATA[60]} {axis_tx_data_TDATA[61]} {axis_tx_data_TDATA[62]} {axis_tx_data_TDATA[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {axis_rx_data_TDATA[0]} {axis_rx_data_TDATA[1]} {axis_rx_data_TDATA[2]} {axis_rx_data_TDATA[3]} {axis_rx_data_TDATA[4]} {axis_rx_data_TDATA[5]} {axis_rx_data_TDATA[6]} {axis_rx_data_TDATA[7]} {axis_rx_data_TDATA[8]} {axis_rx_data_TDATA[9]} {axis_rx_data_TDATA[10]} {axis_rx_data_TDATA[11]} {axis_rx_data_TDATA[12]} {axis_rx_data_TDATA[13]} {axis_rx_data_TDATA[14]} {axis_rx_data_TDATA[15]} {axis_rx_data_TDATA[16]} {axis_rx_data_TDATA[17]} {axis_rx_data_TDATA[18]} {axis_rx_data_TDATA[19]} {axis_rx_data_TDATA[20]} {axis_rx_data_TDATA[21]} {axis_rx_data_TDATA[22]} {axis_rx_data_TDATA[23]} {axis_rx_data_TDATA[24]} {axis_rx_data_TDATA[25]} {axis_rx_data_TDATA[26]} {axis_rx_data_TDATA[27]} {axis_rx_data_TDATA[28]} {axis_rx_data_TDATA[29]} {axis_rx_data_TDATA[30]} {axis_rx_data_TDATA[31]} {axis_rx_data_TDATA[32]} {axis_rx_data_TDATA[33]} {axis_rx_data_TDATA[34]} {axis_rx_data_TDATA[35]} {axis_rx_data_TDATA[36]} {axis_rx_data_TDATA[37]} {axis_rx_data_TDATA[38]} {axis_rx_data_TDATA[39]} {axis_rx_data_TDATA[40]} {axis_rx_data_TDATA[41]} {axis_rx_data_TDATA[42]} {axis_rx_data_TDATA[43]} {axis_rx_data_TDATA[44]} {axis_rx_data_TDATA[45]} {axis_rx_data_TDATA[46]} {axis_rx_data_TDATA[47]} {axis_rx_data_TDATA[48]} {axis_rx_data_TDATA[49]} {axis_rx_data_TDATA[50]} {axis_rx_data_TDATA[51]} {axis_rx_data_TDATA[52]} {axis_rx_data_TDATA[53]} {axis_rx_data_TDATA[54]} {axis_rx_data_TDATA[55]} {axis_rx_data_TDATA[56]} {axis_rx_data_TDATA[57]} {axis_rx_data_TDATA[58]} {axis_rx_data_TDATA[59]} {axis_rx_data_TDATA[60]} {axis_rx_data_TDATA[61]} {axis_rx_data_TDATA[62]} {axis_rx_data_TDATA[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 512 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {mem_inf_inst/ht_m_axis_read_tdata[0]} {mem_inf_inst/ht_m_axis_read_tdata[1]} {mem_inf_inst/ht_m_axis_read_tdata[2]} {mem_inf_inst/ht_m_axis_read_tdata[3]} {mem_inf_inst/ht_m_axis_read_tdata[4]} {mem_inf_inst/ht_m_axis_read_tdata[5]} {mem_inf_inst/ht_m_axis_read_tdata[6]} {mem_inf_inst/ht_m_axis_read_tdata[7]} {mem_inf_inst/ht_m_axis_read_tdata[8]} {mem_inf_inst/ht_m_axis_read_tdata[9]} {mem_inf_inst/ht_m_axis_read_tdata[10]} {mem_inf_inst/ht_m_axis_read_tdata[11]} {mem_inf_inst/ht_m_axis_read_tdata[12]} {mem_inf_inst/ht_m_axis_read_tdata[13]} {mem_inf_inst/ht_m_axis_read_tdata[14]} {mem_inf_inst/ht_m_axis_read_tdata[15]} {mem_inf_inst/ht_m_axis_read_tdata[16]} {mem_inf_inst/ht_m_axis_read_tdata[17]} {mem_inf_inst/ht_m_axis_read_tdata[18]} {mem_inf_inst/ht_m_axis_read_tdata[19]} {mem_inf_inst/ht_m_axis_read_tdata[20]} {mem_inf_inst/ht_m_axis_read_tdata[21]} {mem_inf_inst/ht_m_axis_read_tdata[22]} {mem_inf_inst/ht_m_axis_read_tdata[23]} {mem_inf_inst/ht_m_axis_read_tdata[24]} {mem_inf_inst/ht_m_axis_read_tdata[25]} {mem_inf_inst/ht_m_axis_read_tdata[26]} {mem_inf_inst/ht_m_axis_read_tdata[27]} {mem_inf_inst/ht_m_axis_read_tdata[28]} {mem_inf_inst/ht_m_axis_read_tdata[29]} {mem_inf_inst/ht_m_axis_read_tdata[30]} {mem_inf_inst/ht_m_axis_read_tdata[31]} {mem_inf_inst/ht_m_axis_read_tdata[32]} {mem_inf_inst/ht_m_axis_read_tdata[33]} {mem_inf_inst/ht_m_axis_read_tdata[34]} {mem_inf_inst/ht_m_axis_read_tdata[35]} {mem_inf_inst/ht_m_axis_read_tdata[36]} {mem_inf_inst/ht_m_axis_read_tdata[37]} {mem_inf_inst/ht_m_axis_read_tdata[38]} {mem_inf_inst/ht_m_axis_read_tdata[39]} {mem_inf_inst/ht_m_axis_read_tdata[40]} {mem_inf_inst/ht_m_axis_read_tdata[41]} {mem_inf_inst/ht_m_axis_read_tdata[42]} {mem_inf_inst/ht_m_axis_read_tdata[43]} {mem_inf_inst/ht_m_axis_read_tdata[44]} {mem_inf_inst/ht_m_axis_read_tdata[45]} {mem_inf_inst/ht_m_axis_read_tdata[46]} {mem_inf_inst/ht_m_axis_read_tdata[47]} {mem_inf_inst/ht_m_axis_read_tdata[48]} {mem_inf_inst/ht_m_axis_read_tdata[49]} {mem_inf_inst/ht_m_axis_read_tdata[50]} {mem_inf_inst/ht_m_axis_read_tdata[51]} {mem_inf_inst/ht_m_axis_read_tdata[52]} {mem_inf_inst/ht_m_axis_read_tdata[53]} {mem_inf_inst/ht_m_axis_read_tdata[54]} {mem_inf_inst/ht_m_axis_read_tdata[55]} {mem_inf_inst/ht_m_axis_read_tdata[56]} {mem_inf_inst/ht_m_axis_read_tdata[57]} {mem_inf_inst/ht_m_axis_read_tdata[58]} {mem_inf_inst/ht_m_axis_read_tdata[59]} {mem_inf_inst/ht_m_axis_read_tdata[60]} {mem_inf_inst/ht_m_axis_read_tdata[61]} {mem_inf_inst/ht_m_axis_read_tdata[62]} {mem_inf_inst/ht_m_axis_read_tdata[63]} {mem_inf_inst/ht_m_axis_read_tdata[64]} {mem_inf_inst/ht_m_axis_read_tdata[65]} {mem_inf_inst/ht_m_axis_read_tdata[66]} {mem_inf_inst/ht_m_axis_read_tdata[67]} {mem_inf_inst/ht_m_axis_read_tdata[68]} {mem_inf_inst/ht_m_axis_read_tdata[69]} {mem_inf_inst/ht_m_axis_read_tdata[70]} {mem_inf_inst/ht_m_axis_read_tdata[71]} {mem_inf_inst/ht_m_axis_read_tdata[72]} {mem_inf_inst/ht_m_axis_read_tdata[73]} {mem_inf_inst/ht_m_axis_read_tdata[74]} {mem_inf_inst/ht_m_axis_read_tdata[75]} {mem_inf_inst/ht_m_axis_read_tdata[76]} {mem_inf_inst/ht_m_axis_read_tdata[77]} {mem_inf_inst/ht_m_axis_read_tdata[78]} {mem_inf_inst/ht_m_axis_read_tdata[79]} {mem_inf_inst/ht_m_axis_read_tdata[80]} {mem_inf_inst/ht_m_axis_read_tdata[81]} {mem_inf_inst/ht_m_axis_read_tdata[82]} {mem_inf_inst/ht_m_axis_read_tdata[83]} {mem_inf_inst/ht_m_axis_read_tdata[84]} {mem_inf_inst/ht_m_axis_read_tdata[85]} {mem_inf_inst/ht_m_axis_read_tdata[86]} {mem_inf_inst/ht_m_axis_read_tdata[87]} {mem_inf_inst/ht_m_axis_read_tdata[88]} {mem_inf_inst/ht_m_axis_read_tdata[89]} {mem_inf_inst/ht_m_axis_read_tdata[90]} {mem_inf_inst/ht_m_axis_read_tdata[91]} {mem_inf_inst/ht_m_axis_read_tdata[92]} {mem_inf_inst/ht_m_axis_read_tdata[93]} {mem_inf_inst/ht_m_axis_read_tdata[94]} {mem_inf_inst/ht_m_axis_read_tdata[95]} {mem_inf_inst/ht_m_axis_read_tdata[96]} {mem_inf_inst/ht_m_axis_read_tdata[97]} {mem_inf_inst/ht_m_axis_read_tdata[98]} {mem_inf_inst/ht_m_axis_read_tdata[99]} {mem_inf_inst/ht_m_axis_read_tdata[100]} {mem_inf_inst/ht_m_axis_read_tdata[101]} {mem_inf_inst/ht_m_axis_read_tdata[102]} {mem_inf_inst/ht_m_axis_read_tdata[103]} {mem_inf_inst/ht_m_axis_read_tdata[104]} {mem_inf_inst/ht_m_axis_read_tdata[105]} {mem_inf_inst/ht_m_axis_read_tdata[106]} {mem_inf_inst/ht_m_axis_read_tdata[107]} {mem_inf_inst/ht_m_axis_read_tdata[108]} {mem_inf_inst/ht_m_axis_read_tdata[109]} {mem_inf_inst/ht_m_axis_read_tdata[110]} {mem_inf_inst/ht_m_axis_read_tdata[111]} {mem_inf_inst/ht_m_axis_read_tdata[112]} {mem_inf_inst/ht_m_axis_read_tdata[113]} {mem_inf_inst/ht_m_axis_read_tdata[114]} {mem_inf_inst/ht_m_axis_read_tdata[115]} {mem_inf_inst/ht_m_axis_read_tdata[116]} {mem_inf_inst/ht_m_axis_read_tdata[117]} {mem_inf_inst/ht_m_axis_read_tdata[118]} {mem_inf_inst/ht_m_axis_read_tdata[119]} {mem_inf_inst/ht_m_axis_read_tdata[120]} {mem_inf_inst/ht_m_axis_read_tdata[121]} {mem_inf_inst/ht_m_axis_read_tdata[122]} {mem_inf_inst/ht_m_axis_read_tdata[123]} {mem_inf_inst/ht_m_axis_read_tdata[124]} {mem_inf_inst/ht_m_axis_read_tdata[125]} {mem_inf_inst/ht_m_axis_read_tdata[126]} {mem_inf_inst/ht_m_axis_read_tdata[127]} {mem_inf_inst/ht_m_axis_read_tdata[128]} {mem_inf_inst/ht_m_axis_read_tdata[129]} {mem_inf_inst/ht_m_axis_read_tdata[130]} {mem_inf_inst/ht_m_axis_read_tdata[131]} {mem_inf_inst/ht_m_axis_read_tdata[132]} {mem_inf_inst/ht_m_axis_read_tdata[133]} {mem_inf_inst/ht_m_axis_read_tdata[134]} {mem_inf_inst/ht_m_axis_read_tdata[135]} {mem_inf_inst/ht_m_axis_read_tdata[136]} {mem_inf_inst/ht_m_axis_read_tdata[137]} {mem_inf_inst/ht_m_axis_read_tdata[138]} {mem_inf_inst/ht_m_axis_read_tdata[139]} {mem_inf_inst/ht_m_axis_read_tdata[140]} {mem_inf_inst/ht_m_axis_read_tdata[141]} {mem_inf_inst/ht_m_axis_read_tdata[142]} {mem_inf_inst/ht_m_axis_read_tdata[143]} {mem_inf_inst/ht_m_axis_read_tdata[144]} {mem_inf_inst/ht_m_axis_read_tdata[145]} {mem_inf_inst/ht_m_axis_read_tdata[146]} {mem_inf_inst/ht_m_axis_read_tdata[147]} {mem_inf_inst/ht_m_axis_read_tdata[148]} {mem_inf_inst/ht_m_axis_read_tdata[149]} {mem_inf_inst/ht_m_axis_read_tdata[150]} {mem_inf_inst/ht_m_axis_read_tdata[151]} {mem_inf_inst/ht_m_axis_read_tdata[152]} {mem_inf_inst/ht_m_axis_read_tdata[153]} {mem_inf_inst/ht_m_axis_read_tdata[154]} {mem_inf_inst/ht_m_axis_read_tdata[155]} {mem_inf_inst/ht_m_axis_read_tdata[156]} {mem_inf_inst/ht_m_axis_read_tdata[157]} {mem_inf_inst/ht_m_axis_read_tdata[158]} {mem_inf_inst/ht_m_axis_read_tdata[159]} {mem_inf_inst/ht_m_axis_read_tdata[160]} {mem_inf_inst/ht_m_axis_read_tdata[161]} {mem_inf_inst/ht_m_axis_read_tdata[162]} {mem_inf_inst/ht_m_axis_read_tdata[163]} {mem_inf_inst/ht_m_axis_read_tdata[164]} {mem_inf_inst/ht_m_axis_read_tdata[165]} {mem_inf_inst/ht_m_axis_read_tdata[166]} {mem_inf_inst/ht_m_axis_read_tdata[167]} {mem_inf_inst/ht_m_axis_read_tdata[168]} {mem_inf_inst/ht_m_axis_read_tdata[169]} {mem_inf_inst/ht_m_axis_read_tdata[170]} {mem_inf_inst/ht_m_axis_read_tdata[171]} {mem_inf_inst/ht_m_axis_read_tdata[172]} {mem_inf_inst/ht_m_axis_read_tdata[173]} {mem_inf_inst/ht_m_axis_read_tdata[174]} {mem_inf_inst/ht_m_axis_read_tdata[175]} {mem_inf_inst/ht_m_axis_read_tdata[176]} {mem_inf_inst/ht_m_axis_read_tdata[177]} {mem_inf_inst/ht_m_axis_read_tdata[178]} {mem_inf_inst/ht_m_axis_read_tdata[179]} {mem_inf_inst/ht_m_axis_read_tdata[180]} {mem_inf_inst/ht_m_axis_read_tdata[181]} {mem_inf_inst/ht_m_axis_read_tdata[182]} {mem_inf_inst/ht_m_axis_read_tdata[183]} {mem_inf_inst/ht_m_axis_read_tdata[184]} {mem_inf_inst/ht_m_axis_read_tdata[185]} {mem_inf_inst/ht_m_axis_read_tdata[186]} {mem_inf_inst/ht_m_axis_read_tdata[187]} {mem_inf_inst/ht_m_axis_read_tdata[188]} {mem_inf_inst/ht_m_axis_read_tdata[189]} {mem_inf_inst/ht_m_axis_read_tdata[190]} {mem_inf_inst/ht_m_axis_read_tdata[191]} {mem_inf_inst/ht_m_axis_read_tdata[192]} {mem_inf_inst/ht_m_axis_read_tdata[193]} {mem_inf_inst/ht_m_axis_read_tdata[194]} {mem_inf_inst/ht_m_axis_read_tdata[195]} {mem_inf_inst/ht_m_axis_read_tdata[196]} {mem_inf_inst/ht_m_axis_read_tdata[197]} {mem_inf_inst/ht_m_axis_read_tdata[198]} {mem_inf_inst/ht_m_axis_read_tdata[199]} {mem_inf_inst/ht_m_axis_read_tdata[200]} {mem_inf_inst/ht_m_axis_read_tdata[201]} {mem_inf_inst/ht_m_axis_read_tdata[202]} {mem_inf_inst/ht_m_axis_read_tdata[203]} {mem_inf_inst/ht_m_axis_read_tdata[204]} {mem_inf_inst/ht_m_axis_read_tdata[205]} {mem_inf_inst/ht_m_axis_read_tdata[206]} {mem_inf_inst/ht_m_axis_read_tdata[207]} {mem_inf_inst/ht_m_axis_read_tdata[208]} {mem_inf_inst/ht_m_axis_read_tdata[209]} {mem_inf_inst/ht_m_axis_read_tdata[210]} {mem_inf_inst/ht_m_axis_read_tdata[211]} {mem_inf_inst/ht_m_axis_read_tdata[212]} {mem_inf_inst/ht_m_axis_read_tdata[213]} {mem_inf_inst/ht_m_axis_read_tdata[214]} {mem_inf_inst/ht_m_axis_read_tdata[215]} {mem_inf_inst/ht_m_axis_read_tdata[216]} {mem_inf_inst/ht_m_axis_read_tdata[217]} {mem_inf_inst/ht_m_axis_read_tdata[218]} {mem_inf_inst/ht_m_axis_read_tdata[219]} {mem_inf_inst/ht_m_axis_read_tdata[220]} {mem_inf_inst/ht_m_axis_read_tdata[221]} {mem_inf_inst/ht_m_axis_read_tdata[222]} {mem_inf_inst/ht_m_axis_read_tdata[223]} {mem_inf_inst/ht_m_axis_read_tdata[224]} {mem_inf_inst/ht_m_axis_read_tdata[225]} {mem_inf_inst/ht_m_axis_read_tdata[226]} {mem_inf_inst/ht_m_axis_read_tdata[227]} {mem_inf_inst/ht_m_axis_read_tdata[228]} {mem_inf_inst/ht_m_axis_read_tdata[229]} {mem_inf_inst/ht_m_axis_read_tdata[230]} {mem_inf_inst/ht_m_axis_read_tdata[231]} {mem_inf_inst/ht_m_axis_read_tdata[232]} {mem_inf_inst/ht_m_axis_read_tdata[233]} {mem_inf_inst/ht_m_axis_read_tdata[234]} {mem_inf_inst/ht_m_axis_read_tdata[235]} {mem_inf_inst/ht_m_axis_read_tdata[236]} {mem_inf_inst/ht_m_axis_read_tdata[237]} {mem_inf_inst/ht_m_axis_read_tdata[238]} {mem_inf_inst/ht_m_axis_read_tdata[239]} {mem_inf_inst/ht_m_axis_read_tdata[240]} {mem_inf_inst/ht_m_axis_read_tdata[241]} {mem_inf_inst/ht_m_axis_read_tdata[242]} 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{mem_inf_inst/ht_m_axis_read_tdata[267]} {mem_inf_inst/ht_m_axis_read_tdata[268]} {mem_inf_inst/ht_m_axis_read_tdata[269]} {mem_inf_inst/ht_m_axis_read_tdata[270]} {mem_inf_inst/ht_m_axis_read_tdata[271]} {mem_inf_inst/ht_m_axis_read_tdata[272]} {mem_inf_inst/ht_m_axis_read_tdata[273]} {mem_inf_inst/ht_m_axis_read_tdata[274]} {mem_inf_inst/ht_m_axis_read_tdata[275]} {mem_inf_inst/ht_m_axis_read_tdata[276]} {mem_inf_inst/ht_m_axis_read_tdata[277]} {mem_inf_inst/ht_m_axis_read_tdata[278]} {mem_inf_inst/ht_m_axis_read_tdata[279]} {mem_inf_inst/ht_m_axis_read_tdata[280]} {mem_inf_inst/ht_m_axis_read_tdata[281]} {mem_inf_inst/ht_m_axis_read_tdata[282]} {mem_inf_inst/ht_m_axis_read_tdata[283]} {mem_inf_inst/ht_m_axis_read_tdata[284]} {mem_inf_inst/ht_m_axis_read_tdata[285]} {mem_inf_inst/ht_m_axis_read_tdata[286]} {mem_inf_inst/ht_m_axis_read_tdata[287]} {mem_inf_inst/ht_m_axis_read_tdata[288]} {mem_inf_inst/ht_m_axis_read_tdata[289]} {mem_inf_inst/ht_m_axis_read_tdata[290]} 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{mem_inf_inst/ht_m_axis_read_tdata[363]} {mem_inf_inst/ht_m_axis_read_tdata[364]} {mem_inf_inst/ht_m_axis_read_tdata[365]} {mem_inf_inst/ht_m_axis_read_tdata[366]} {mem_inf_inst/ht_m_axis_read_tdata[367]} {mem_inf_inst/ht_m_axis_read_tdata[368]} {mem_inf_inst/ht_m_axis_read_tdata[369]} {mem_inf_inst/ht_m_axis_read_tdata[370]} {mem_inf_inst/ht_m_axis_read_tdata[371]} {mem_inf_inst/ht_m_axis_read_tdata[372]} {mem_inf_inst/ht_m_axis_read_tdata[373]} {mem_inf_inst/ht_m_axis_read_tdata[374]} {mem_inf_inst/ht_m_axis_read_tdata[375]} {mem_inf_inst/ht_m_axis_read_tdata[376]} {mem_inf_inst/ht_m_axis_read_tdata[377]} {mem_inf_inst/ht_m_axis_read_tdata[378]} {mem_inf_inst/ht_m_axis_read_tdata[379]} {mem_inf_inst/ht_m_axis_read_tdata[380]} {mem_inf_inst/ht_m_axis_read_tdata[381]} {mem_inf_inst/ht_m_axis_read_tdata[382]} {mem_inf_inst/ht_m_axis_read_tdata[383]} {mem_inf_inst/ht_m_axis_read_tdata[384]} {mem_inf_inst/ht_m_axis_read_tdata[385]} {mem_inf_inst/ht_m_axis_read_tdata[386]} {mem_inf_inst/ht_m_axis_read_tdata[387]} {mem_inf_inst/ht_m_axis_read_tdata[388]} {mem_inf_inst/ht_m_axis_read_tdata[389]} {mem_inf_inst/ht_m_axis_read_tdata[390]} {mem_inf_inst/ht_m_axis_read_tdata[391]} {mem_inf_inst/ht_m_axis_read_tdata[392]} {mem_inf_inst/ht_m_axis_read_tdata[393]} {mem_inf_inst/ht_m_axis_read_tdata[394]} {mem_inf_inst/ht_m_axis_read_tdata[395]} {mem_inf_inst/ht_m_axis_read_tdata[396]} {mem_inf_inst/ht_m_axis_read_tdata[397]} {mem_inf_inst/ht_m_axis_read_tdata[398]} {mem_inf_inst/ht_m_axis_read_tdata[399]} {mem_inf_inst/ht_m_axis_read_tdata[400]} {mem_inf_inst/ht_m_axis_read_tdata[401]} {mem_inf_inst/ht_m_axis_read_tdata[402]} {mem_inf_inst/ht_m_axis_read_tdata[403]} {mem_inf_inst/ht_m_axis_read_tdata[404]} {mem_inf_inst/ht_m_axis_read_tdata[405]} {mem_inf_inst/ht_m_axis_read_tdata[406]} {mem_inf_inst/ht_m_axis_read_tdata[407]} {mem_inf_inst/ht_m_axis_read_tdata[408]} {mem_inf_inst/ht_m_axis_read_tdata[409]} {mem_inf_inst/ht_m_axis_read_tdata[410]} {mem_inf_inst/ht_m_axis_read_tdata[411]} {mem_inf_inst/ht_m_axis_read_tdata[412]} {mem_inf_inst/ht_m_axis_read_tdata[413]} {mem_inf_inst/ht_m_axis_read_tdata[414]} {mem_inf_inst/ht_m_axis_read_tdata[415]} {mem_inf_inst/ht_m_axis_read_tdata[416]} {mem_inf_inst/ht_m_axis_read_tdata[417]} {mem_inf_inst/ht_m_axis_read_tdata[418]} {mem_inf_inst/ht_m_axis_read_tdata[419]} {mem_inf_inst/ht_m_axis_read_tdata[420]} {mem_inf_inst/ht_m_axis_read_tdata[421]} {mem_inf_inst/ht_m_axis_read_tdata[422]} {mem_inf_inst/ht_m_axis_read_tdata[423]} {mem_inf_inst/ht_m_axis_read_tdata[424]} {mem_inf_inst/ht_m_axis_read_tdata[425]} {mem_inf_inst/ht_m_axis_read_tdata[426]} {mem_inf_inst/ht_m_axis_read_tdata[427]} {mem_inf_inst/ht_m_axis_read_tdata[428]} {mem_inf_inst/ht_m_axis_read_tdata[429]} {mem_inf_inst/ht_m_axis_read_tdata[430]} {mem_inf_inst/ht_m_axis_read_tdata[431]} {mem_inf_inst/ht_m_axis_read_tdata[432]} {mem_inf_inst/ht_m_axis_read_tdata[433]} {mem_inf_inst/ht_m_axis_read_tdata[434]} {mem_inf_inst/ht_m_axis_read_tdata[435]} {mem_inf_inst/ht_m_axis_read_tdata[436]} {mem_inf_inst/ht_m_axis_read_tdata[437]} {mem_inf_inst/ht_m_axis_read_tdata[438]} {mem_inf_inst/ht_m_axis_read_tdata[439]} {mem_inf_inst/ht_m_axis_read_tdata[440]} {mem_inf_inst/ht_m_axis_read_tdata[441]} {mem_inf_inst/ht_m_axis_read_tdata[442]} {mem_inf_inst/ht_m_axis_read_tdata[443]} {mem_inf_inst/ht_m_axis_read_tdata[444]} {mem_inf_inst/ht_m_axis_read_tdata[445]} {mem_inf_inst/ht_m_axis_read_tdata[446]} {mem_inf_inst/ht_m_axis_read_tdata[447]} {mem_inf_inst/ht_m_axis_read_tdata[448]} {mem_inf_inst/ht_m_axis_read_tdata[449]} {mem_inf_inst/ht_m_axis_read_tdata[450]} {mem_inf_inst/ht_m_axis_read_tdata[451]} {mem_inf_inst/ht_m_axis_read_tdata[452]} {mem_inf_inst/ht_m_axis_read_tdata[453]} {mem_inf_inst/ht_m_axis_read_tdata[454]} {mem_inf_inst/ht_m_axis_read_tdata[455]} {mem_inf_inst/ht_m_axis_read_tdata[456]} {mem_inf_inst/ht_m_axis_read_tdata[457]} {mem_inf_inst/ht_m_axis_read_tdata[458]} {mem_inf_inst/ht_m_axis_read_tdata[459]} {mem_inf_inst/ht_m_axis_read_tdata[460]} {mem_inf_inst/ht_m_axis_read_tdata[461]} {mem_inf_inst/ht_m_axis_read_tdata[462]} {mem_inf_inst/ht_m_axis_read_tdata[463]} {mem_inf_inst/ht_m_axis_read_tdata[464]} {mem_inf_inst/ht_m_axis_read_tdata[465]} {mem_inf_inst/ht_m_axis_read_tdata[466]} {mem_inf_inst/ht_m_axis_read_tdata[467]} {mem_inf_inst/ht_m_axis_read_tdata[468]} {mem_inf_inst/ht_m_axis_read_tdata[469]} {mem_inf_inst/ht_m_axis_read_tdata[470]} {mem_inf_inst/ht_m_axis_read_tdata[471]} {mem_inf_inst/ht_m_axis_read_tdata[472]} {mem_inf_inst/ht_m_axis_read_tdata[473]} {mem_inf_inst/ht_m_axis_read_tdata[474]} {mem_inf_inst/ht_m_axis_read_tdata[475]} {mem_inf_inst/ht_m_axis_read_tdata[476]} {mem_inf_inst/ht_m_axis_read_tdata[477]} {mem_inf_inst/ht_m_axis_read_tdata[478]} {mem_inf_inst/ht_m_axis_read_tdata[479]} {mem_inf_inst/ht_m_axis_read_tdata[480]} {mem_inf_inst/ht_m_axis_read_tdata[481]} {mem_inf_inst/ht_m_axis_read_tdata[482]} {mem_inf_inst/ht_m_axis_read_tdata[483]} {mem_inf_inst/ht_m_axis_read_tdata[484]} {mem_inf_inst/ht_m_axis_read_tdata[485]} {mem_inf_inst/ht_m_axis_read_tdata[486]} {mem_inf_inst/ht_m_axis_read_tdata[487]} {mem_inf_inst/ht_m_axis_read_tdata[488]} {mem_inf_inst/ht_m_axis_read_tdata[489]} {mem_inf_inst/ht_m_axis_read_tdata[490]} {mem_inf_inst/ht_m_axis_read_tdata[491]} {mem_inf_inst/ht_m_axis_read_tdata[492]} {mem_inf_inst/ht_m_axis_read_tdata[493]} {mem_inf_inst/ht_m_axis_read_tdata[494]} {mem_inf_inst/ht_m_axis_read_tdata[495]} {mem_inf_inst/ht_m_axis_read_tdata[496]} {mem_inf_inst/ht_m_axis_read_tdata[497]} {mem_inf_inst/ht_m_axis_read_tdata[498]} {mem_inf_inst/ht_m_axis_read_tdata[499]} {mem_inf_inst/ht_m_axis_read_tdata[500]} {mem_inf_inst/ht_m_axis_read_tdata[501]} {mem_inf_inst/ht_m_axis_read_tdata[502]} {mem_inf_inst/ht_m_axis_read_tdata[503]} {mem_inf_inst/ht_m_axis_read_tdata[504]} {mem_inf_inst/ht_m_axis_read_tdata[505]} {mem_inf_inst/ht_m_axis_read_tdata[506]} {mem_inf_inst/ht_m_axis_read_tdata[507]} {mem_inf_inst/ht_m_axis_read_tdata[508]} {mem_inf_inst/ht_m_axis_read_tdata[509]} {mem_inf_inst/ht_m_axis_read_tdata[510]} {mem_inf_inst/ht_m_axis_read_tdata[511]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 80 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {mem_inf_inst/upd_s_axis_read_cmd_tdata[0]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[1]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[2]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[3]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[4]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[5]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[6]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[7]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[8]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[9]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[10]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[11]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[12]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[13]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[14]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[15]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[16]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[17]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[18]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[19]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[20]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[21]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[22]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[23]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[24]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[25]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[26]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[27]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[28]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[29]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[30]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[31]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[32]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[33]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[34]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[35]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[36]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[37]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[38]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[39]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[40]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[41]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[42]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[43]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[44]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[45]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[46]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[47]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[48]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[49]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[50]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[51]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[52]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[53]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[54]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[55]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[56]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[57]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[58]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[59]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[60]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[61]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[62]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[63]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[64]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[65]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[66]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[67]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[68]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[69]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[70]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[71]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[72]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[73]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[74]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[75]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[76]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[77]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[78]} {mem_inf_inst/upd_s_axis_read_cmd_tdata[79]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 80 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {mem_inf_inst/ht_s_axis_read_cmd_tdata[0]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[1]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[2]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[3]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[4]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[5]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[6]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[7]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[8]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[9]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[10]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[11]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[12]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[13]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[14]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[15]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[16]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[17]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[18]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[19]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[20]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[21]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[22]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[23]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[24]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[25]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[26]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[27]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[28]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[29]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[30]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[31]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[32]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[33]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[34]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[35]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[36]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[37]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[38]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[39]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[40]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[41]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[42]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[43]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[44]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[45]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[46]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[47]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[48]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[49]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[50]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[51]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[52]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[53]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[54]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[55]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[56]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[57]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[58]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[59]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[60]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[61]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[62]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[63]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[64]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[65]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[66]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[67]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[68]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[69]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[70]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[71]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[72]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[73]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[74]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[75]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[76]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[77]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[78]} {mem_inf_inst/ht_s_axis_read_cmd_tdata[79]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 80 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {mem_inf_inst/upd_s_axis_write_cmd_tdata[0]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[1]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[2]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[3]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[4]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[5]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[6]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[7]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[8]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[9]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[10]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[11]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[12]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[13]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[14]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[15]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[16]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[17]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[18]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[19]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[20]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[21]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[22]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[23]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[24]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[25]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[26]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[27]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[28]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[29]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[30]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[31]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[32]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[33]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[34]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[35]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[36]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[37]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[38]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[39]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[40]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[41]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[42]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[43]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[44]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[45]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[46]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[47]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[48]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[49]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[50]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[51]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[52]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[53]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[54]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[55]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[56]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[57]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[58]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[59]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[60]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[61]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[62]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[63]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[64]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[65]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[66]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[67]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[68]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[69]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[70]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[71]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[72]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[73]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[74]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[75]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[76]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[77]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[78]} {mem_inf_inst/upd_s_axis_write_cmd_tdata[79]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list axis_rx_data_TLAST]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list axis_rx_data_TREADY]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list axis_rx_data_TVALID]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list axis_tx_data_TLAST]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list axis_tx_data_TREADY]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list axis_tx_data_TVALID]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list multiuser_kvs_top/muukvs_instance/feedbwhash_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list multiuser_kvs_top/muukvs_instance/feedbwhash_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list multiuser_kvs_top/muukvs_instance/fromset_b_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list multiuser_kvs_top/muukvs_instance/fromset_b_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list multiuser_kvs_top/muukvs_instance/fromset_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list multiuser_kvs_top/muukvs_instance/fromset_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list multiuser_kvs_top/muukvs_instance/hashaddr_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list multiuser_kvs_top/muukvs_instance/hashaddr_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list ht_cmd_dramRdData_stall]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list ht_cmd_dramRdData_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list ht_cmd_dramWrData_stall]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list ht_cmd_dramWrData_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list mem_inf_inst/ht_m_axis_read_tready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list mem_inf_inst/ht_s_axis_read_cmd_tready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list mem_inf_inst/ht_s_axis_read_cmd_tvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list multiuser_kvs_top/muukvs_instance/key_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list multiuser_kvs_top/muukvs_instance/key_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list multiuser_kvs_top/muukvs_instance/keywhash_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list multiuser_kvs_top/muukvs_instance/keywhash_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
connect_debug_port u_ila_0/probe36 [get_nets [list multiuser_kvs_top/muukvs_instance/malloc_error_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
connect_debug_port u_ila_0/probe37 [get_nets [list multiuser_kvs_top/muukvs_instance/meta_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
connect_debug_port u_ila_0/probe38 [get_nets [list multiuser_kvs_top/muukvs_instance/meta_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
connect_debug_port u_ila_0/probe39 [get_nets [list multiuser_kvs_top/muukvs_instance/outputErrorHead]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
connect_debug_port u_ila_0/probe40 [get_nets [list multiuser_kvs_top/muukvs_instance/secondhash_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
connect_debug_port u_ila_0/probe41 [get_nets [list multiuser_kvs_top/muukvs_instance/secondhash_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
connect_debug_port u_ila_0/probe42 [get_nets [list multiuser_kvs_top/muukvs_instance/tohash_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
connect_debug_port u_ila_0/probe43 [get_nets [list multiuser_kvs_top/muukvs_instance/tohash_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
connect_debug_port u_ila_0/probe44 [get_nets [list multiuser_kvs_top/muukvs_instance/towrite_b_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
connect_debug_port u_ila_0/probe45 [get_nets [list multiuser_kvs_top/muukvs_instance/towrite_b_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
connect_debug_port u_ila_0/probe46 [get_nets [list upd_cmd_dramRdData_stall]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
connect_debug_port u_ila_0/probe47 [get_nets [list upd_cmd_dramRdData_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
connect_debug_port u_ila_0/probe48 [get_nets [list upd_cmd_dramWrData_stall]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
connect_debug_port u_ila_0/probe49 [get_nets [list upd_cmd_dramWrData_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
connect_debug_port u_ila_0/probe50 [get_nets [list mem_inf_inst/upd_m_axis_read_sts_tvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
connect_debug_port u_ila_0/probe51 [get_nets [list mem_inf_inst/upd_m_axis_write_sts_tvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
connect_debug_port u_ila_0/probe52 [get_nets [list mem_inf_inst/upd_s_axis_read_cmd_tready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
connect_debug_port u_ila_0/probe53 [get_nets [list mem_inf_inst/upd_s_axis_read_cmd_tvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
connect_debug_port u_ila_0/probe54 [get_nets [list mem_inf_inst/upd_s_axis_write_cmd_tready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
connect_debug_port u_ila_0/probe55 [get_nets [list mem_inf_inst/upd_s_axis_write_cmd_tvalid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
connect_debug_port u_ila_0/probe56 [get_nets [list multiuser_kvs_top/muukvs_instance/value_last]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
connect_debug_port u_ila_0/probe57 [get_nets [list multiuser_kvs_top/muukvs_instance/value_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
connect_debug_port u_ila_0/probe58 [get_nets [list multiuser_kvs_top/muukvs_instance/value_valid]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
connect_debug_port u_ila_0/probe59 [get_nets [list multiuser_kvs_top/muukvs_instance/writeout_ready]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
connect_debug_port u_ila_0/probe60 [get_nets [list multiuser_kvs_top/muukvs_instance/writeout_valid]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
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// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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