Commit ae8eda53 authored by Zsolt Istvan's avatar Zsolt Istvan
Browse files

Initial copy of files for multi-tenant version.

parent 6b10fdcf
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module muu_Checkpoint #(
parameter DATA_WIDTH = 192,
parameter USER_BITS = 3,
parameter FIFO_BITS = 6,
parameter COST_BITS = 16,
parameter BURST_BITS = 12,
parameter LIMIT_PER_USER = 8,
parameter TB_DEFAULT_DEPTH = 160,
parameter TB_DEFAULT_UPDFREQ = 1,
parameter TB_DEFAULT_UPDCOUNT = 2,
parameter TB_DEFAULT_HEADER_SIZE = 2+7
)
(
// Clock
input wire clk,
input wire rst,
input wire[DATA_WIDTH-1:0] in_data,
input wire in_valid,
input wire[USER_BITS-1:0] in_user,
input wire[COST_BITS-1:0] in_cost,
input wire in_first,
input wire in_last,
output wire in_ready,
output wire[DATA_WIDTH-1:0] out_data,
output wire out_valid,
output wire[USER_BITS-1:0] out_user,
output wire out_first,
output wire out_last,
input wire out_ready,
input wire config_valid,
input wire[15:0] config_burst,
input wire[USER_BITS-1:0] config_user,
input wire[7:0] config_updfreq,
input wire[7:0] config_updcount,
input wire decrement_valid,
input wire[USER_BITS-1:0] decrement_user
);
wire inValidNow;
wire [2**USER_BITS-1:0] queueInReady;
assign inValidNow = (queueInReady == {2**USER_BITS {1'b1}} ) ? in_valid : 0;
assign in_ready = (queueInReady == {2**USER_BITS {1'b1}} ) ? 1 : 0;
reg [7:0] userOpsCount [0:2**USER_BITS-1];
wire [2**USER_BITS-1:0] queueOutReady;
wire [2**USER_BITS-1:0] queueOutValid;
wire [2**USER_BITS-1:0] queueOutTake;
wire [2+DATA_WIDTH+COST_BITS-1:0] queueOutData [0:2**USER_BITS-1];
wire [2**USER_BITS-1:0] regInReady;
wire [2**USER_BITS-1:0] regInValid;
wire [2+DATA_WIDTH-1:0] regInData [0:2**USER_BITS-1];
wire [2**USER_BITS-1:0] regOutReady;
wire [2**USER_BITS-1:0] regOutValid;
wire [2+DATA_WIDTH-1:0] regOutData [0:2**USER_BITS-1];
reg [2**USER_BITS-1:0] limitReached;
reg [USER_BITS-1:0] currentSel;
reg[DATA_WIDTH-1:0] out_i_data;
reg out_i_valid;
reg[USER_BITS-1:0] out_i_user;
reg out_i_first;
reg out_i_last;
wire out_i_ready;
wire[COST_BITS-1:0] curCost;
wire[USER_BITS-1:0] curUser;
assign curCost = (in_valid==1 && in_first==1) ? in_cost : curCost;
assign curUser = (in_valid==1 && in_first==1) ? in_user : curUser;
generate
genvar i;
for (i=0; i<2**USER_BITS; i=i+1) begin
nukv_fifogen #(
.DATA_SIZE(DATA_WIDTH+COST_BITS+2),
.ADDR_BITS(FIFO_BITS)
) fifo_mod (
.clk(clk),
.rst(rst),
.s_axis_tdata({in_last,in_first,curCost,in_data}),
.s_axis_tvalid((inValidNow==1 && curUser==i) ? 1 : 0),
.s_axis_tready(queueInReady[i]),
.m_axis_tdata(queueOutData[i]),
.m_axis_tvalid(queueOutValid[i]),
.m_axis_tready(queueOutReady[i])
);
muu_TokenBucket #(
.DATA_WIDTH(DATA_WIDTH+2),
.DEFAULT_DEPTH(TB_DEFAULT_DEPTH),
.DEFAULT_UPDFREQ(TB_DEFAULT_UPDFREQ),
.DEFAULT_UPDCOUNT(TB_DEFAULT_UPDCOUNT),
.DEFAULT_HEADER_SIZE(TB_DEFAULT_HEADER_SIZE)
)
token_bucket (
.clk(clk),
.rst(rst),
.limit_reached(limitReached[i]),
.take_valid(queueOutValid[i] & queueOutData[i][DATA_WIDTH+COST_BITS]),
.take_cont(queueOutValid[i] & ~queueOutData[i][DATA_WIDTH+COST_BITS] ),
.take_size({{16-COST_BITS{1'b0}},queueOutData[i][DATA_WIDTH+COST_BITS-1 : DATA_WIDTH]}),
.take_data({queueOutData[i][DATA_WIDTH+COST_BITS +: 2],queueOutData[i][DATA_WIDTH-1:0]}),
.take_ready(queueOutReady[i]),
.take_allow_valid(regInValid[i]),
.take_allow_ready(regInReady[i]),
.take_allow_data(regInData[i]),
.config_valid((config_valid==1 && config_user==i) ? 1 : 0),
.config_depth(config_burst),
.config_updcount(config_updcount),
.config_updfreq(config_updfreq)
);
kvs_LatchedRelay #(
.WIDTH(DATA_WIDTH+2)
) smallreg (
.clk(clk),
.rst(rst),
.in_valid(regInValid[i]),
.in_data(regInData[i]),
.in_ready(regInReady[i]),
.out_valid(regOutValid[i]),
.out_ready(regOutReady[i]),
.out_data(regOutData[i])
);
assign regOutReady[i] = (currentSel==i) ? out_i_ready : 0;
end
endgenerate
reg [USER_BITS-1:0] nextSel;
integer q;
integer aset;
always @(posedge clk) begin
if (rst) begin
currentSel <= 0;
nextSel <= 0;
for (q=0; q<2**USER_BITS; q=q+1) begin
userOpsCount[q] <= 0;
limitReached[q] <= 0;
end
out_i_valid <= 0;
end
else begin
if (out_i_valid==1 && out_i_ready==1) begin
out_i_valid <= 0;
end
if (out_i_valid==0 || out_i_ready==1) begin
out_i_user <= currentSel;
out_i_data <= regOutData[currentSel][DATA_WIDTH-1:0];
out_i_valid <= regOutValid[currentSel] & regOutReady[currentSel];
out_i_last <= regOutData[currentSel][DATA_WIDTH+1];
out_i_first <= regOutData[currentSel][DATA_WIDTH];
end
if (LIMIT_PER_USER>0) begin
if (decrement_valid==1 && userOpsCount[decrement_user]>0) begin
userOpsCount[decrement_user] <= userOpsCount[decrement_user]-1;
if (userOpsCount[decrement_user]<=LIMIT_PER_USER) begin
limitReached[decrement_user] <= 0;
end
end
if (out_i_valid==1 && out_i_ready==1 && out_i_first==1) begin
userOpsCount[out_i_user] <= userOpsCount[out_i_user]+1;
if (userOpsCount[out_i_user]>=LIMIT_PER_USER-1) begin
limitReached[out_i_user] <= 1;
end
if (decrement_valid==1 && decrement_user==out_i_user) begin
userOpsCount[out_i_user] <= userOpsCount[out_i_user];
limitReached[out_i_user] <= limitReached[out_i_user];
end
end
end
if ((out_i_ready==1 && out_i_valid==1 && out_i_last==1 && regOutValid[currentSel]==0) || (regOutValid[currentSel]==0 && out_i_valid==0)) begin
currentSel <= currentSel+1;
aset = 0;
for (q=1; q<2**USER_BITS && aset==0; q=q+1) begin
if (regOutValid[(currentSel+q)%(2**USER_BITS)]==1) begin
currentSel <= currentSel+q;
aset = 666;
end
end
end
end
end
kvs_LatchedRelay #(
.WIDTH(DATA_WIDTH+USER_BITS+2)
) finalout (
.clk(clk),
.rst(rst),
.in_valid(out_i_valid),
.in_data({out_i_last,out_i_first,out_i_user,out_i_data}),
.in_ready(out_i_ready),
.out_valid(out_valid),
.out_ready(out_ready),
.out_data({out_last,out_first,out_user,out_data})
);
endmodule
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module muu_DataRepeater #(
parameter DATA_WIDTH = 512,
parameter DATA_DEPTH = 16
)
(
// Clock
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output reg s_axis_tready,
input wire [7:0] config_count,
input wire [7:0] config_size,
input wire config_valid,
output reg config_ready,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready
);
reg [DATA_WIDTH-1:0] intMemory [DATA_DEPTH-1:0];
reg working;
reg [7:0] wordsLeft;
reg [7:0] repsLeft;
reg [7:0] readsCount;
reg [7:0] readsLeft;
wire outready;
wire outvalid;
kvs_LatchedRelay #(
.WIDTH(DATA_WIDTH)
) output_reg (
.clk(clk),
.rst(rst),
.in_valid(outvalid),
.in_ready(outready),
.in_data(intMemory[wordsLeft]),
.out_valid(m_axis_tvalid),
.out_ready(m_axis_tready),
.out_data(m_axis_tdata)
);
assign outvalid = outready & working & (readsLeft<=wordsLeft);
always @ (posedge clk)
if(rst)
begin
wordsLeft <= 0;
repsLeft <= 0;
working <= 0;
config_ready <= 0;
s_axis_tready <= 0;
end
else begin
if (wordsLeft==0 && repsLeft==0 && config_ready==0 && working==0) begin
config_ready <= 1;
end
if (config_ready==1 && config_valid==1) begin
repsLeft <= config_count-1;
wordsLeft <= config_size-1;
readsLeft <= config_size;
readsCount <= config_size;
config_ready <= 0;
s_axis_tready <= 1;
end
if (s_axis_tready==1 && s_axis_tvalid==1) begin
working <= 1;
intMemory[readsLeft-1] <= s_axis_tdata;
readsLeft <= readsLeft-1;
if (readsLeft==1) begin
readsLeft <= 0;
s_axis_tready <= 0;
end
end
if (outready==1 && outvalid==1) begin
wordsLeft <= wordsLeft-1;
if (wordsLeft==0) begin
repsLeft <= repsLeft-1;
wordsLeft <= readsCount-1;
if (repsLeft==0) begin
working <= 0;
repsLeft <= 0;
wordsLeft <= 0;
end
end
end
end // else
endmodule // muu_DataRepeater
\ No newline at end of file
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module muu_HT_Read #(
parameter KEY_WIDTH = 128,
parameter META_WIDTH = 96,
parameter HASHADDR_WIDTH = 64,
parameter MEMADDR_WIDTH = 21,
parameter USER_BITS = 3
)
(
// Clock
input wire clk,
input wire rst,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH+USER_BITS-1:0] input_data,
input wire input_valid,
output wire input_ready,
input wire [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH+USER_BITS-1:0] feedback_data,
input wire feedback_valid,
output wire feedback_ready,
output reg [KEY_WIDTH+META_WIDTH+HASHADDR_WIDTH+USER_BITS-1:0] output_data,
output reg output_valid,
input wire output_ready,
output reg [31:0] rdcmd_data,
output reg rdcmd_valid,
input wire rdcmd_ready
);
reg selectInputNext;
reg selectInput; //1 == input, 0==feedback
localparam [2:0]
ST_IDLE = 0,
ST_ISSUE_READ_ONE = 1,
ST_ISSUE_READ_TWO = 2,
ST_OUTPUT_KEY = 3;
reg [2:0] state;
wire[HASHADDR_WIDTH+KEY_WIDTH+META_WIDTH+USER_BITS-1:0] in_data;
wire in_valid;
reg in_ready;
wire[HASHADDR_WIDTH-1:0] hash_data;
wire [USER_BITS-1:0] curr_user;
assign in_data = (selectInput==1) ? input_data : feedback_data;
assign in_valid = (selectInput==1) ? input_valid : feedback_valid;
assign input_ready = (selectInput==1) ? in_ready : 0;
assign feedback_ready = (selectInput==1) ? 0 : in_ready;
assign curr_user = (selectInput==1) ? input_data[KEY_WIDTH+META_WIDTH+USER_BITS-1:KEY_WIDTH+META_WIDTH] : feedback_data[KEY_WIDTH+META_WIDTH+USER_BITS-1:KEY_WIDTH+META_WIDTH];
assign hash_data = (selectInput==1) ? input_data[KEY_WIDTH+META_WIDTH+USER_BITS+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH+USER_BITS] : feedback_data[KEY_WIDTH+META_WIDTH+USER_BITS+HASHADDR_WIDTH-1:KEY_WIDTH+META_WIDTH+USER_BITS];
wire[MEMADDR_WIDTH-1:0] addr1;
wire[MEMADDR_WIDTH-1:0] addr2;
assign addr1 = hash_data[0 +: HASHADDR_WIDTH/2];
assign addr2 = hash_data[HASHADDR_WIDTH/2 +: HASHADDR_WIDTH/2];
always @(posedge clk) begin
if (rst) begin
selectInput <= 1;
selectInputNext <= 0;
state <= ST_IDLE;
in_ready <= 0;
rdcmd_valid <= 0;
output_valid <= 0;
end
else begin
if (rdcmd_ready==1 && rdcmd_valid==1) begin
rdcmd_valid <= 0;
end
if (output_ready==1 && output_valid==1) begin
output_valid <= 0;
end
in_ready <= 0;
case (state)
ST_IDLE : begin
if (output_ready==1 && rdcmd_ready==1) begin
selectInput <= selectInputNext;
selectInputNext <= ~selectInputNext;
if (selectInputNext==1 && input_valid==0 && feedback_valid==1) begin
selectInput <= 0;
selectInputNext <= 1;
end
if (selectInputNext==0 && input_valid==1 && feedback_valid==0) begin
selectInput <= 1;
selectInputNext <= 0;
end
if (selectInput==1 && input_valid==1) begin
state <= ST_ISSUE_READ_ONE;
end
if (selectInput==0 && feedback_valid==1) begin
state <= ST_ISSUE_READ_ONE;
end
end
end
ST_ISSUE_READ_ONE: begin
state <= ST_ISSUE_READ_TWO;
output_data <= in_data;
if (in_data[KEY_WIDTH+META_WIDTH-8 +: 4]==0 || in_data[KEY_WIDTH+META_WIDTH-8 +: 4]==7) begin
// ignore this and don't send read!
in_ready <= 1;
state <= ST_OUTPUT_KEY;
end else begin
rdcmd_data[MEMADDR_WIDTH-1:0] <= {curr_user, addr1[MEMADDR_WIDTH-USER_BITS-1:0]};
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
end
ST_ISSUE_READ_TWO: begin
if (rdcmd_ready==1) begin
state <= ST_OUTPUT_KEY;
in_ready <= 1;
rdcmd_data[MEMADDR_WIDTH-1:0] <= {curr_user, addr2[MEMADDR_WIDTH-USER_BITS-1:0]};
rdcmd_valid <= 1;
rdcmd_data[31:MEMADDR_WIDTH] <= 0;
end
end
ST_OUTPUT_KEY: begin
if (output_ready==1) begin
output_valid <= 1;
state <= ST_IDLE;
end
end
endcase
end
end
endmodule
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//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------