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Commit b74023c7 authored by Zsolt István's avatar Zsolt István
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Fixed bug in kickout logic that could get stuck trying the same address... 

Fixed  bug in kickout logic that could get stuck trying the same address because of the ff_memory; also increased the hasher parallelism, added some more backpressure protection
parent 768c8db5
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hw/src/muu/muu_dedup_hashers.v
View file @ b74023c7
......@@ -32,7 +32,7 @@ module muu_Dedup_Hashers
);
parameter HASH_COUNT_BITS = 4;
parameter MAX_HASH_ENGINES = 9;
parameter MAX_HASH_ENGINES = 16;
wire [512:0] hash_input_data [MAX_HASH_ENGINES-1:0];
reg [512:0] hash_input_prebuf [MAX_HASH_ENGINES-1:0];
......@@ -47,7 +47,7 @@ reg softReset;
reg softResetInt;
wire [MAX_HASH_ENGINES-1:0] hash_output_valid;
wire [63:0] hash_output_data [MAX_HASH_ENGINES-1:0];
wire [511:0] hash_output_data [MAX_HASH_ENGINES-1:0];
wire [MAX_HASH_ENGINES-1:0] outfifo_valid;
wire [MAX_HASH_ENGINES-1:0] outfifo_ready;
......@@ -123,7 +123,7 @@ generate
nukv_fifogen #(
.DATA_SIZE(513),
.ADDR_BITS(4)
.ADDR_BITS(6)
)
fifo_values (
.clk(clk),
......
hw/src/muu/muu_ht_write_dedup.v
View file @ b74023c7
......@@ -119,15 +119,14 @@ reg [FASTFORWARD_BITS-1:0] pos_ff;
reg [1:0] found_ff;
reg [1:0] found_addr_ff;
reg [1:0] empty_ff;
reg [FASTFORWARD_BITS-1:0] found_ff_pos;
reg [1:0] found_ff_idx;
reg [1:0] empty_ff_idx;
reg [1:0] found_ff_idx [0:1];
reg [1:0] empty_ff_idx [0:1];
reg found_kk;
reg [FASTFORWARD_BITS-1:0] found_kk_pos;
reg [1:0] found_mem;
reg [1:0] found_mem_idx;
reg [1:0] found_mem_idx [0:1];
reg [1:0] empty_mem;
reg [1:0] empty_mem_idx;
reg [1:0] empty_mem_idx [0:1];
reg [31:0] oldpointer;
......@@ -175,7 +174,7 @@ integer c;
integer x;
reg[USER_BITS+MEMORY_WIDTH-1:0] fastforward_mem_pos_reg;
reg[USER_BITS+MEMORY_WIDTH-1:0] fastforward_mem_found_reg;
reg[USER_BITS+MEMORY_WIDTH-1:0] fastforward_mem_found_reg [0:1];
reg [USER_BITS+KEY_WIDTH+HEADER_WIDTH-1:0] kicked_keys_pos_reg;
reg [USER_BITS+KEY_WIDTH+HEADER_WIDTH-1:0] kicked_keys_found_reg;
......@@ -189,7 +188,7 @@ reg kicked_keys_write_valid;
reg[511:0] write_data_prep;
reg[MEMORY_WIDTH-1:0] rdMemWord [1:2];
reg[MEMORY_WIDTH-1:0] rdMemWord [0:1];
reg mallocRegValid;
reg[31:0] mallocRegData;
......@@ -199,6 +198,10 @@ reg[15:0] inputValueSize;
reg rst_regd;
reg[4:0] random_num;
reg random_pick;
reg[1:0] random_idx;
always @(posedge clk) begin
rst_regd <= rst;
......@@ -234,14 +237,26 @@ always @(posedge clk) begin
malloc_ready <= 0;
empty_ff_idx <= 0;
empty_mem_idx <= 0;
empty_ff_idx[0] <= 0;
empty_mem_idx[0] <= 0;
empty_ff_idx[1] <= 0;
empty_mem_idx[1] <= 0;
prev_opmode <= HTOP_IGNORE;
random_num <= 5'b10101;
end
else begin
random_num <= { random_num[3:0], random_num[4] ^ random_num[3] };
if (random_num==5'b00000 || random_num==5'b11111) begin
random_num <= {ff_head[3:0],1'b1};
end
random_pick <= random_num[0];
random_idx <= random_num[2:1];
fastforward_mem_pos_reg <= fastforward_mem[pos_ff];
kicked_keys_pos_reg <= kicked_keys[pos_kk];
......@@ -381,11 +396,11 @@ always @(posedge clk) begin
ST_CHECK_FF: begin
if (pos_ff==(ff_head+1)%2**FASTFORWARD_BITS && pos_kk==(kk_head+1)%2**FASTFORWARD_BITS) begin
if (found_addr_ff!=0) begin
state <= ST_SKIP_MEM;
end else begin
//if (found_addr_ff!=0) begin
// state <= ST_SKIP_MEM;
//end else begin
state <= ST_CHECK_MEM;
end
//end
end else begin
if (pos_ff!=(ff_head+1)%2**FASTFORWARD_BITS) begin
......@@ -393,49 +408,41 @@ always @(posedge clk) begin
if (pos_ff!=ff_tail) begin
if (fastforward_addr[pos_ff-1]==curr_hash1 && fastforward_mem_pos_reg[MEMORY_WIDTH+USER_BITS-1:MEMORY_WIDTH]==curr_user) begin
found_addr_ff <= 1;
found_ff_pos <= pos_ff-1;
fastforward_mem_found_reg <= fastforward_mem_pos_reg;
found_ff_idx <= 0;
empty_ff <= 0;
found_addr_ff[0] <= 1;
fastforward_mem_found_reg[0] <= fastforward_mem_pos_reg;
found_ff_idx[0] <= 0;
empty_ff[0] <= 0;
// compare to this data
for (c=0; c<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); c=c+1) begin
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_ff <= 1;
found_ff_pos <= pos_ff-1;
found_ff_idx <= c;
end else begin
found_ff <= 0;
end
found_ff[0] <= 1;
found_ff_idx[0] <= c;
end
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0) begin
empty_ff_idx <= c;
empty_ff <= 1;
empty_ff_idx[0] <= c;
empty_ff[0] <= 1;
end
end
end
if (fastforward_addr[pos_ff-1]==curr_hash2 && fastforward_mem_pos_reg[MEMORY_WIDTH+USER_BITS-1:MEMORY_WIDTH]==curr_user) begin
found_addr_ff <= 2;
found_ff_pos <= pos_ff-1;
fastforward_mem_found_reg <= fastforward_mem_pos_reg;
found_ff_idx <= 0;
empty_ff <= 0;
found_addr_ff[1] <= 1;
fastforward_mem_found_reg[1] <= fastforward_mem_pos_reg;
found_ff_idx[1] <= 0;
empty_ff[1] <= 0;
// compare to this data
for (c=0; c<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); c=c+1) begin
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_ff <= 2;
found_ff_pos <= pos_ff-1;
found_ff_idx <= c;
end else begin
found_ff <= 0;
end
found_ff[1] <= 1;
found_ff_idx[1] <= c;
end
if (fastforward_mem_pos_reg[(c)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0) begin
empty_ff_idx <= c;
empty_ff <= 2;
empty_ff_idx[1] <= c;
empty_ff[1] <= 1;
end
end
end
......@@ -496,12 +503,12 @@ always @(posedge clk) begin
for (x=0; x<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); x=x+1) begin
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_mem <= 1;
found_mem_idx <= x;
found_mem[0] <= 1;
found_mem_idx[0] <= x;
end
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0) begin
empty_mem_idx <= x;
empty_mem <= 1;
empty_mem_idx[0] <= x;
empty_mem[0] <= 1;
end
end
......@@ -523,7 +530,7 @@ always @(posedge clk) begin
rd_ready <= 1;
rdMemWord[1] <= rd_data;
rdMemWord[0] <= rd_data;
state <= ST_CHECK_MEM_TWO;
end
......@@ -533,18 +540,18 @@ always @(posedge clk) begin
if (rd_ready==0 && rd_valid==1) begin
// compare to this data
rdMemWord[2] <= rd_data;
rdMemWord[1] <= rd_data;
for (x=0; x<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH); x=x+1) begin
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==inputReg[KEY_WIDTH-1:0]) begin
found_mem <= 2;
found_mem_idx <= x;
found_mem[1] <= 1;
found_mem_idx[1] <= x;
end
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0 && empty_mem==0) begin
empty_mem_idx <= x;
empty_mem <= 2;
if (rd_data[(x)*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH]==0 && empty_mem[1]==0) begin
empty_mem_idx[1] <= x;
empty_mem[1] <= 1;
end
end
......@@ -567,83 +574,140 @@ always @(posedge clk) begin
writebackLine <= 0;
writebackToKK <= 1;
end else if (found_addr_ff!=0) begin
writebackEntry <= {curr_user , fastforward_mem_found_reg[found_ff_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackLine <= fastforward_mem_found_reg;
if (found_ff==1) begin
end else if (found_addr_ff!=0 && found_ff!=0) begin
if (found_ff[0]==1) begin
writebackAddr <= curr_hash1;
writebackIdx <= found_ff_idx;
writebackIdx <= found_ff_idx[0];
writebackKeyMatch <= 1;
writebackEntry <= {curr_user , fastforward_mem_found_reg[0][found_ff_idx[0]*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackLine <= fastforward_mem_found_reg[0];
end else if (found_ff==2) begin
end else if (found_ff[1]==1) begin
writebackAddr <= curr_hash2;
writebackIdx <= found_ff_idx;
writebackIdx <= found_ff_idx[1];
writebackKeyMatch <= 1;
writebackEntry <= {curr_user , fastforward_mem_found_reg[1][found_ff_idx[1]*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackLine <= fastforward_mem_found_reg[1];
end
end else if (found_addr_ff[0]==0 && found_mem[0]==1) begin
writebackAddr <= curr_hash1;
writebackIdx <= found_mem_idx[0];
writebackEntry <= {curr_user, rdMemWord[0][found_mem_idx[0]*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackKeyMatch <= 1;
writebackLine <= rdMemWord[0];
end else if (empty_ff==1) begin
end else if (found_addr_ff[1]==0 && found_mem[1]==1) begin
writebackAddr <= curr_hash2;
writebackIdx <= found_mem_idx[1];
writebackEntry <= {curr_user, rdMemWord[1][found_mem_idx[1]*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackKeyMatch <= 1;
writebackLine <= rdMemWord[1];
end else if (((~found_addr_ff) & empty_mem)!=0) begin
if (found_addr_ff[0]==0 && empty_mem[0]==1) begin
writebackAddr <= curr_hash1;
writebackIdx <= empty_ff_idx;
writebackEntry <= 0;
writebackIdx <= empty_mem_idx[0];
writebackLine <= rdMemWord[0];
writebackKeyMatch <= 0;
end else if (empty_ff==2) begin
writebackAddr <= curr_hash2;
writebackIdx <= empty_ff_idx;
writebackEntry <= 0;
writebackKeyMatch <= 0;
end else begin
writebackAddr <= curr_hash2;
writebackIdx <= empty_mem_idx[1];
writebackLine <= rdMemWord[1];
writebackKeyMatch <= 0;
writebackEntry <= 0;
end
end else if (random_pick==0) begin
if (found_addr_ff[0]==1) begin
writebackAddr <= found_addr_ff==1 ? curr_hash1 : curr_hash2;
writebackLine <= fastforward_mem_found_reg[0];
if (ff_tail[1:0]<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= ff_tail[1:0];
writebackEntry <= {curr_user, fastforward_mem_found_reg[ff_tail[1:0]*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
if (empty_ff[0]==1) begin
writebackAddr <= curr_hash1;
writebackIdx <= empty_ff_idx[0];
writebackEntry <= 0;
writebackKeyMatch <= 0;
end else begin
writebackAddr <= curr_hash1;
if (random_idx<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= random_idx;
writebackEntry <= {curr_user, fastforward_mem_found_reg[0][random_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end else begin
writebackIdx <= 0;
writebackEntry <= {curr_user, fastforward_mem_found_reg[0][0*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end
writebackKeyMatch <= 0;
writebackNeedsKick <= 1;
end
end else begin
writebackAddr <= curr_hash1;
if (random_idx<<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= random_idx;
writebackEntry <= {curr_user, rdMemWord[0][random_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end else begin
writebackIdx <= 0;
writebackEntry <= {curr_user, fastforward_mem_found_reg[0*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackEntry <= {curr_user, rdMemWord[0][0*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end
writebackKeyMatch <= 0;
writebackLine <= rdMemWord[0];
writebackNeedsKick <= 1;
end
end else begin
end else if (found_mem!=0) begin
if (found_addr_ff[1]==1) begin
writebackAddr <= (found_mem==1) ? curr_hash1 : curr_hash2;
writebackIdx <= found_mem_idx;
writebackEntry <= {curr_user, rdMemWord[found_mem][found_mem_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackKeyMatch <= 1;
writebackLine <= rdMemWord[found_mem];
writebackLine <= fastforward_mem_found_reg[1];
end else if (empty_mem!=0) begin
if (empty_ff[1]==1) begin
writebackAddr <= curr_hash2;
writebackIdx <= empty_ff_idx[1];
writebackEntry <= 0;
writebackKeyMatch <= 0;
end else begin
writebackAddr <= curr_hash2;
writebackAddr <= (empty_mem==1) ? curr_hash1 : curr_hash2;
writebackIdx <= empty_mem_idx;
writebackLine <= rdMemWord[empty_mem];
writebackKeyMatch <= 0;
writebackEntry <= 0;
if (random_idx<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= random_idx;
writebackEntry <= {curr_user, fastforward_mem_found_reg[1][random_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end else begin
writebackIdx <= 0;
writebackEntry <= {curr_user, fastforward_mem_found_reg[1][0*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end
end else begin
writebackKeyMatch <= 0;
writebackNeedsKick <= 1;
end
end else begin
writebackAddr <= curr_hash2;
writebackAddr <= curr_hash1;
if (random_idx<<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= random_idx;
writebackEntry <= {curr_user, rdMemWord[1][random_idx*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end else begin
writebackIdx <= 0;
writebackEntry <= {curr_user, rdMemWord[1][0*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end
if (ff_tail[1:0]<MEMORY_WIDTH/(KEY_WIDTH+HEADER_WIDTH)) begin
writebackIdx <= ff_tail[1:0];
writebackEntry <= {curr_user, rdMemWord[1][ff_tail[1:0]*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
end else begin
writebackIdx <= 0;
writebackEntry <= {curr_user, rdMemWord[1][0*(KEY_WIDTH+HEADER_WIDTH) +: KEY_WIDTH+HEADER_WIDTH]};
writebackKeyMatch <= 0;
writebackLine <= rdMemWord[1];
writebackNeedsKick <= 1;
end
writebackKeyMatch <= 0;
writebackLine <= rdMemWord[1];
writebackNeedsKick <= 1;
end
end
state <= ST_DECIDE;
......
hw/src/muu/muu_top_module_lmem_dedup.v
View file @ b74023c7
......@@ -154,8 +154,8 @@ parameter SUPPORT_SCANS = 0;
parameter FILTER_ENABLED_NUM = FILTER_REGEX_PARA + FILTER_PRED_CNT;
wire [31:0] rdcmd_data;
wire rdcmd_valid;
(* mark_debug = "true" *)wire [31:0] rdcmd_data;
(* mark_debug = "true" *)wire rdcmd_valid;
wire rdcmd_stall;
wire rdcmd_ready;
......@@ -213,7 +213,7 @@ wire [EXT_META_WIDTH-1:0] meta_data;
(* mark_debug = "true" *)wire meta_ready;
wire [USER_BITS+63:0] tohash_data;
wire [127:0] tohash_data;
(* mark_debug = "true" *)wire tohash_valid;
(* mark_debug = "true" *)wire tohash_ready;
......@@ -375,7 +375,7 @@ wire sh_in_buf_ready;
wire sh_in_ready;
wire sh_in_valid;
wire sh_in_choice;
wire[63+USER_BITS:0] sh_in_data;
wire[127:0] sh_in_data;
wire write_feedback_channel_ready;
......@@ -647,17 +647,22 @@ nukv_fifogen #(
.m_axis_tready(tosm_ready)
);
(* mark_debug = "true" *)wire value_mainbuf_ready;
(* mark_debug = "true" *)wire value_shabuf_ready;
assign value_ready = value_mainbuf_ready & value_shabuf_ready;
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH+16+1),
.ADDR_BITS(8) //!!!
.ADDR_BITS(10) //!!! 16* 2^6
) fifo_value (
.clk(clk),
.rst(rst),
.s_axis_tdata({value_last, value_length, value_data}),
.s_axis_tvalid(value_valid),
.s_axis_tready(value_ready),
.s_axis_talmostfull(value_almost_full),
.s_axis_tvalid(value_valid & value_ready),
.s_axis_tready(value_mainbuf_ready),
.s_axis_talmostfull(),
.m_axis_tdata(value_b_data),
.m_axis_tvalid(value_b_valid),
......@@ -673,16 +678,18 @@ wire[63:0] value_hash_data;
(* mark_debug = "true" *)wire value_hash_valid;
(* mark_debug = "true" *)wire value_hash_ready;
assign value_almost_full = value_prehash_valid & ~value_prehash_ready;
nukv_fifogen #(
.DATA_SIZE(513),
.ADDR_BITS(8) //!!!
.ADDR_BITS(4) //!!!
) fifo_value_hash (
.clk(clk),
.rst(rst),
.s_axis_tdata({value_last, value_data}),
.s_axis_tvalid(value_valid & value_ready),
.s_axis_tready(),
.s_axis_tready(value_shabuf_ready),
.s_axis_talmostfull(),
.m_axis_tdata({value_prehash_last,value_prehash_data}),
......@@ -965,7 +972,7 @@ nukv_fifogen #(
.s_axis_tvalid(cmd_out_valid_g),
.s_axis_tready(cmd_out_key_ready),
.m_axis_tdata(tohash_data),
.m_axis_tdata(tohash_data[KEY_WIDTH+USER_BITS-1:0]),
.m_axis_tvalid(tohash_valid),
.m_axis_tready(tohash_ready)
);
......@@ -973,13 +980,14 @@ nukv_fifogen #(
assign value_b_length = value_b_data[VALUE_WIDTH +: 16];
assign value_b_last = value_b_data[VALUE_WIDTH+16];
assign tohash_data[127:KEY_WIDTH+USER_BITS] = 0;
wire [31:0] h1addr1;
wire [31:0] h1addr2;
wire [USER_BITS-1:0] h1user;
assign h1user = tohash_data[KEY_WIDTH +: USER_BITS];
assign h1addr1 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h1user,tohash_data[0 +: HASHTABLE_MEM_SIZE] ^ tohash_data[64-HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign h1addr2 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h1user,tohash_data[0 +: HASHTABLE_MEM_SIZE] ^ tohash_data[HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign h1addr1 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h1user,tohash_data[0 +: HASHTABLE_MEM_SIZE]^tohash_data[2*HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign h1addr2 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h1user,tohash_data[HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign fromhash_valid = tohash_valid;
assign tohash_ready = fromhash_ready;
......@@ -1038,17 +1046,19 @@ nukv_fifogen #(
.s_axis_tvalid(write_feedback_channel_ready & writefb_valid),
.s_axis_tready(sh_in_buf_ready),
.m_axis_tdata(sh_in_data),
.m_axis_tdata(sh_in_data[KEY_WIDTH+USER_BITS-1:0]),
.m_axis_tvalid(sh_in_valid),
.m_axis_tready(sh_in_ready)
);
assign sh_in_data[127:KEY_WIDTH+USER_BITS] = 0;
wire [31:0] h2addr1;
wire [31:0] h2addr2;
wire [USER_BITS-1:0] h2user;
assign h2user = sh_in_data[KEY_WIDTH +: USER_BITS];
assign h2addr1 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h2user,sh_in_data[0 +: HASHTABLE_MEM_SIZE] ^ sh_in_data[64-HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign h2addr2 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h2user,sh_in_data[0 +: HASHTABLE_MEM_SIZE] ^ sh_in_data[HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign h2addr1 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h2user,sh_in_data[0 +: HASHTABLE_MEM_SIZE]^sh_in_data[2*HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign h2addr2 = {{32-USER_BITS-HASHTABLE_MEM_SIZE{1'b0}},h2user,sh_in_data[HASHTABLE_MEM_SIZE +: HASHTABLE_MEM_SIZE]};
assign secondhash_valid = sh_in_valid;
assign sh_in_ready = secondhash_ready;
......
hw/src/nukv/nukv_malloc_v2.v
View file @ b74023c7
......@@ -22,7 +22,7 @@ module nukv_Malloc #(
parameter BLOCKSIZE = 64, //B,
parameter REQSIZE = 1, //B
parameter MAX_MEMORY_SIZE = 24,
parameter CLASS_COUNT = 5,
parameter CLASS_COUNT = 8,
parameter SUPPORT_SCANS = 1,
parameter IS_SIM = 0
)
......@@ -134,7 +134,10 @@ module nukv_Malloc #(
CLASS1 = 1,
CLASS2 = 2,
CLASS3 = 4,
CLASS4 = 8;
CLASS4 = 8,
CLASS5 = 16,
CLASS6 = 32,
CLASS7 = 64;
localparam integer REFILL_BUFF_BITS = (IS_SIM==0 ? 6 : 4);
......@@ -339,9 +342,9 @@ module nukv_Malloc #(
end else
if (req_valid==1 && req_ready==1) begin
in_class <= (req_data <= CLASS1*BLOCKSIZE) ? 1 : (req_data<=CLASS2*BLOCKSIZE) ? 2 : (req_data<=CLASS3*BLOCKSIZE) ? 3 : (req_data<=CLASS4*BLOCKSIZE) ? 4 : 0;
in_class <= (req_data <= CLASS1*BLOCKSIZE) ? 1 : (req_data<=CLASS2*BLOCKSIZE) ? 2 : (req_data<=CLASS3*BLOCKSIZE) ? 3 : (req_data<=CLASS4*BLOCKSIZE) ? 4 : (req_data<=CLASS5*BLOCKSIZE) ? 5 : (req_data<=CLASS6*BLOCKSIZE) ? 6 : (req_data<=CLASS7*BLOCKSIZE) ? 7 :0;
neededsize <= (req_data <= CLASS1*BLOCKSIZE) ? CLASS1 : (req_data<=CLASS2*BLOCKSIZE) ? CLASS2 : (req_data<=CLASS3*BLOCKSIZE) ? CLASS3 : (req_data<=CLASS4*BLOCKSIZE) ? CLASS4 : 0;
neededsize <= (req_data <= CLASS1*BLOCKSIZE) ? CLASS1 : (req_data<=CLASS2*BLOCKSIZE) ? CLASS2 : (req_data<=CLASS3*BLOCKSIZE) ? CLASS3 : (req_data<=CLASS4*BLOCKSIZE) ? CLASS4 : (req_data<=CLASS5*BLOCKSIZE) ? CLASS5 : (req_data<=CLASS6*BLOCKSIZE) ? CLASS6 : (req_data<=CLASS7*BLOCKSIZE) ? CLASS7 : 0;
have_large_pointers <= (queuevalid[0]==1 || (head_pointer[0]!=tail_pointer[0])) ? 1 : 0;
......
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