migrated to vivado 2018.2 -- upgraded IP

hw/constraints/multiple-nics.xdc

@@ -280,7 +280,7 @@ set_clock_groups -name async_xgemac_clk50 -asynchronous \
    -group [get_clocks clk50]
    
 ####contraints from DRAM MEM inf
-create_clock -period 4.708 -name sys_clk_212 [get_ports sys_clk_p]
+create_clock -period 4.285 -name sys_clk_233 [get_ports sys_clk_p]
 
 set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
 set_property IOSTANDARD DIFF_SSTL15 [get_ports {sys_clk_p}]
@@ -297,7 +297,7 @@ set_property IOSTANDARD LVCMOS18 [get_ports {sys_rst}]
 set_property PACKAGE_PIN AV40 [get_ports {sys_rst}]
 
 # REMOVED WITH DDR3
-set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_212_i]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_233_i]
 
 set_clock_groups -name clk156_pll_i -asynchronous -group [get_clocks clk_pll_i] -group [get_clocks clk156]
 set_clock_groups -name clk156_pll_i_1 -asynchronous -group [get_clocks clk_pll_i_1] -group [get_clocks clk156]

hw/ip/dramsim/fifogen_dram_cmd_in/fifogen_dram_cmd_in.veo

-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
@@ -46,7 +46,7 @@
 // 
 // DO NOT MODIFY THIS FILE.
 
-// IP VLNV: xilinx.com:ip:fifo_generator:12.0
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
 // IP Revision: 2
 
 // The following must be inserted into your Verilog file for this

hw/ip/dramsim/fifogen_dram_data_in/fifogen_dram_data_in.veo

-// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
@@ -46,7 +46,7 @@
 // 
 // DO NOT MODIFY THIS FILE.
 
-// IP VLNV: xilinx.com:ip:fifo_generator:12.0
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
 // IP Revision: 2
 
 // The following must be inserted into your Verilog file for this

hw/ip/dramsim/fifogen_dram_data_out/fifogen_dram_data_out.veo

-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
@@ -46,7 +46,7 @@
 // 
 // DO NOT MODIFY THIS FILE.
 
-// IP VLNV: xilinx.com:ip:fifo_generator:12.0
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
 // IP Revision: 2
 
 // The following must be inserted into your Verilog file for this

hw/ip/muu/fifo_256bit_regslice/fifo_256bit_regslice.veo

+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 2
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_256bit_regslice your_instance_name (
+  .s_aclk(s_aclk),                // input wire s_aclk
+  .s_aresetn(s_aresetn),          // input wire s_aresetn
+  .s_axis_tvalid(s_axis_tvalid),  // input wire s_axis_tvalid
+  .s_axis_tready(s_axis_tready),  // output wire s_axis_tready
+  .s_axis_tdata(s_axis_tdata),    // input wire [255 : 0] s_axis_tdata
+  .m_axis_tvalid(m_axis_tvalid),  // output wire m_axis_tvalid
+  .m_axis_tready(m_axis_tready),  // input wire m_axis_tready
+  .m_axis_tdata(m_axis_tdata)    // output wire [255 : 0] m_axis_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_256bit_regslice.v when simulating
+// the core, fifo_256bit_regslice. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

hw/ip/muu/fifo_512bit_regslice/fifo_512bit_regslice.veo

+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 2
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_512bit_regslice your_instance_name (
+  .s_aclk(s_aclk),                // input wire s_aclk
+  .s_aresetn(s_aresetn),          // input wire s_aresetn
+  .s_axis_tvalid(s_axis_tvalid),  // input wire s_axis_tvalid
+  .s_axis_tready(s_axis_tready),  // output wire s_axis_tready
+  .s_axis_tdata(s_axis_tdata),    // input wire [511 : 0] s_axis_tdata
+  .m_axis_tvalid(m_axis_tvalid),  // output wire m_axis_tvalid
+  .m_axis_tready(m_axis_tready),  // input wire m_axis_tready
+  .m_axis_tdata(m_axis_tdata)    // output wire [511 : 0] m_axis_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_512bit_regslice.v when simulating
+// the core, fifo_512bit_regslice. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

hw/ip/muu/fifo_64bit_regslice/fifo_64bit_regslice.veo

+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 2
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_64bit_regslice your_instance_name (
+  .s_aclk(s_aclk),                // input wire s_aclk
+  .s_aresetn(s_aresetn),          // input wire s_aresetn
+  .s_axis_tvalid(s_axis_tvalid),  // input wire s_axis_tvalid
+  .s_axis_tready(s_axis_tready),  // output wire s_axis_tready
+  .s_axis_tdata(s_axis_tdata),    // input wire [63 : 0] s_axis_tdata
+  .m_axis_tvalid(m_axis_tvalid),  // output wire m_axis_tvalid
+  .m_axis_tready(m_axis_tready),  // input wire m_axis_tready
+  .m_axis_tdata(m_axis_tdata)    // output wire [63 : 0] m_axis_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_64bit_regslice.v when simulating
+// the core, fifo_64bit_regslice. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

hw/ip/system/axi_kvs_mem_interconnect_3/axi_kvs_mem_interconnect_3.veo

-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
@@ -47,7 +47,7 @@
 // DO NOT MODIFY THIS FILE.
 
 // IP VLNV: xilinx.com:ip:axi_interconnect:1.7
-// IP Revision: 4
+// IP Revision: 14
 
 // The following must be inserted into your Verilog file for this
 // core to be instantiated. Change the instance name and port connections

hw/ip/system/axi_read_kvs_datamover/axi_read_kvs_datamover.veo

-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
@@ -47,7 +47,7 @@
 // DO NOT MODIFY THIS FILE.
 
 // IP VLNV: xilinx.com:ip:axi_datamover:5.1
-// IP Revision: 4
+// IP Revision: 19
 
 // The following must be inserted into your Verilog file for this
 // core to be instantiated. Change the instance name and port connections

hw/ip/system/axi_read_tcp_datamover/axi_read_tcp_datamover.veo

-// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
@@ -47,7 +47,7 @@
 // DO NOT MODIFY THIS FILE.
 
 // IP VLNV: xilinx.com:ip:axi_datamover:5.1
-// IP Revision: 4
+// IP Revision: 19
 
 // The following must be inserted into your Verilog file for this
 // core to be instantiated. Change the instance name and port connections

hw/ip/system/axi_write_kvs_datamover/axi_write_kvs_datamover.veo

-// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
@@ -47,7 +47,7 @@
 // DO NOT MODIFY THIS FILE.
 
 // IP VLNV: xilinx.com:ip:axi_datamover:5.1
-// IP Revision: 4
+// IP Revision: 19
 
 // The following must be inserted into your Verilog file for this
 // core to be instantiated. Change the instance name and port connections