Commit e584bfb6 authored by Zsolt István's avatar Zsolt István
Browse files

added row-to-col reverter

parent 11feb509
module ColToRow #(
parameter COL_BITS = 2,
parameter COL_COUNT = 3,
parameter CNT_SKIP_WORDS = 0,
parameter EQUAL_LENGTH_COMP = 1
parameter CNT_SKIP_WORDS = 0
)
(
input wire clk,
......@@ -96,16 +95,11 @@ always @(posedge clk) begin
end
end
wire [31:0] sum;
genvar X;
generate
if (EQUAL_LENGTH_COMP==1) begin
assign sum=buffer_output_data[0][31:0]+buffer_output_data[1][31:0]+buffer_output_data[2][31:0];
end
for (X=0; X < COL_COUNT; X=X+1)
begin: generateloop
......@@ -128,7 +122,7 @@ generate
.m_axis_tready(buffer_output_ready)
);
assign assembled_data[X*32 +: 32] = (assembled_pos==0 && first_word==1 && EQUAL_LENGTH_COMP==1) ? sum : buffer_output_data[X][assembled_pos*32 +: 32];
assign assembled_data[X*32 +: 32] = buffer_output_data[X][assembled_pos*32 +: 32];
assign assembled_last_pre[X] = buffer_output_data[X][512];
end
endgenerate
......
module RowToCol #(
parameter COL_BITS = 2,
parameter COL_COUNT = 3
)
(
input wire clk,
input wire rst,
input wire [COL_COUNT*32-1:0] input_data,
input wire input_valid,
input wire input_last,
output wire input_ready,
output wire [511:0] output_data,
output wire output_valid,
output wire output_last,
input wire output_ready
);
reg [512:0] buffer_input_data [COL_COUNT-1:0];
wire [COL_COUNT-1:0] buffer_input_almfull;
wire [COL_COUNT-1:0] buffer_input_notfull;
reg [COL_COUNT-1:0] buffer_input_enable;
reg [7:0] buffer_input_words;
wire [512:0] buffer_output_data [COL_COUNT-1:0];
wire [COL_COUNT-1:0] buffer_output_valid;
wire [COL_COUNT-1:0] buffer_output_ready;
reg [COL_COUNT-1:0] buffer_output_sel;
wire input_valid_masked;
assign input_ready = (buffer_input_notfull=={COL_COUNT{1'b1}} && buffer_input_almfull=={COL_COUNT{1'b0}}) ? 1 : 0;
assign input_valid_masked = input_valid & input_ready;
integer x;
always @(posedge clk) begin
if(rst) begin
for (x=0; x<COL_COUNT; x=x+1) begin
buffer_input_data[x] <= 0;
buffer_input_enable[x] <= 0;
end
buffer_input_words <= 0;
end else begin
buffer_input_enable <= 0;
if (input_valid_masked==1) begin
for (x=0; x<COL_COUNT; x=x+1) begin
buffer_input_data[x][buffer_input_words*32 +: 32] <= input_data[x*32 +: 32];
buffer_input_data[x][512] <= input_last;
end
buffer_input_words <= buffer_input_words+1;
if (buffer_input_words==15 || input_last==1) begin
buffer_input_words <= 0;
buffer_input_enable <= {COL_COUNT{1'b1}};
end
end
end
end
genvar X;
generate
for (X=0; X < COL_COUNT; X=X+1)
begin: generateloop
nukv_fifogen #(
.DATA_SIZE(513),
.ADDR_BITS(9)
)
fifo_values (
.clk(clk),
.rst(rstBuf),
.s_axis_tdata(buffer_input_data[X]),
.s_axis_tvalid(buffer_input_enable[X]),
.s_axis_tready(buffer_input_notfull[X]),
.s_axis_talmostfull(buffer_input_almfull[X]),
.m_axis_tdata(buffer_output_data[X][512:0]),
.m_axis_tvalid(buffer_output_valid[X]),
.m_axis_tready(buffer_output_ready[X])
);
assign buffer_output_ready[X] = buffer_output_sel==X ? output_ready : 0;
end
endgenerate
assign output_data = buffer_output_data[buffer_output_sel][511:0];
assign output_last = buffer_output_data[buffer_output_sel][512:0];
assign output_valid = buffer_output_valid[buffer_output_sel];
always @(posedge clk) begin
if(rst) begin
buffer_output_sel <= 0;
end else begin
if (output_ready==1 && output_valid==1 && output_last==1) begin
buffer_output_sel <= buffer_output_sel+1;
if (buffer_output_sel==COL_COUNT-1) begin
buffer_output_sel <= 0;
end
end
end
end
endmodule
\ No newline at end of file
......@@ -17,18 +17,17 @@ module nukv_Rotation_Module
reg[2:0] state;
wire[511:0] ctr_data;
wire[32*3-1:0] ctr_data;
wire ctr_valid;
wire ctr_ready;
wire ctr_last;
reg[511:0] alt_data;
reg alt_valid;
reg alt_last;
wire[511:0] rtc_data;
wire rtc_valid;
wire rtc_ready;
wire rtc_last;
ColToRow #(
.EQUAL_LENGTH_COMP(1)
) rotation_perturb (
ColToRow col_to_row (
.clk(clk),
.rst(rst),
......@@ -43,10 +42,31 @@ module nukv_Rotation_Module
.output_last(ctr_last)
);
assign output_valid = state==0 ? ctr_valid : alt_valid;
assign output_data = state==0 ? ctr_data : alt_data;
assign output_last = state==0 ? ctr_last : alt_last;
assign ctr_ready = state==0 ? output_ready : 0;
RowToCol row_to_col (
.clk(clk),
.rst(rst),
.input_data(ctr_data),
.input_valid(ctr_valid),
.input_ready(ctr_ready),
.input_last(ctr_last),
.output_data(rtc_data),
.output_valid(rtc_valid),
.output_ready(rtc_ready),
.output_last(rtc_last)
);
reg[511:0] alt_data;
reg alt_valid;
reg alt_last;
assign output_valid = state==0 ? rtc_valid : alt_valid;
assign output_data = state==0 ? rtc_data : alt_data;
assign output_last = state==0 ? rtc_last : alt_last;
assign rtc_ready = state==0 ? output_ready : 0;
always @(posedge clk) begin
if(rst) begin
......@@ -57,7 +77,7 @@ module nukv_Rotation_Module
state <= 0;
end else begin
case (state)
/*case (state)
0: begin
if (ctr_valid==1 && output_ready==1 && ctr_last==1) begin
state <= state+1;
......@@ -73,10 +93,11 @@ module nukv_Rotation_Module
state <= 0;
end
end
default : /* default */;
endcase
*/
end
end
endmodule;
\ No newline at end of file
endmodule
\ No newline at end of file
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment