Added Stream sources

backup/summary300/vitis_analyzer.jou

+#-----------------------------------------------------------
+# Vitis Analyzer v2020.1 (64-bit)
+# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
+# 
+# Start of session at: Wed Aug  5 15:59:41 2020
+# Process ID: 8938
+# Current directory: /home/atosa/Documents/RandomGen/backup/summary300
+# Command line: vitis_analyzer rndgen.u250.xclbin.link_summary
+# Log file: /home/atosa/Documents/RandomGen/backup/summary300/vitis_analyzer.log
+# Journal file: /home/atosa/Documents/RandomGen/backup/summary300/vitis_analyzer.jou
+#-----------------------------------------------------------
+start_gui
+create_project dummy

backup/summary300/vitis_analyzer_8380.backup.jou

+#-----------------------------------------------------------
+# Vitis Analyzer v2020.1 (64-bit)
+# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
+# 
+# Start of session at: Wed Aug  5 15:29:09 2020
+# Process ID: 8380
+# Current directory: /home/atosa/Documents/RandomGen/backup/summary300
+# Command line: vitis_analyzer rndgen.u250.xclbin.link_summary
+# Log file: /home/atosa/Documents/RandomGen/backup/summary300/vitis_analyzer.log
+# Journal file: /home/atosa/Documents/RandomGen/backup/summary300/vitis_analyzer.jou
+#-----------------------------------------------------------
+start_gui
+create_project dummy

design.cfg

 platform=xilinx_u250_xdma_201830_2
 debug=1
+save-temps=1
+profile_kernel=data:all:all:all
 
 [connectivity]
 nk=rndgen:1:rndgen_1

profile_kernels.csv

-Compute Units: Running Time and Stalls
-Compute Unit, Running Time (us), Intra-Kernel Dataflow Stalls (%), External Memory Stalls (%), External Stream Stalls (%)
-rndgen_1,0.570,0.000,12.865,0.000
-
-Functions: Running Time and Stalls
-Compute Unit, Function, Running Time (us), Intra-Kernel Dataflow Stalls (%), External Memory Stalls (%), External Stream Stalls (%)
-
-Compute Units: Port Data Transfer
-Compute Unit, Port, Write Time (us), Outstanding Write (%), Read Time (us), Outstanding Read (%)
-rndgen_1,m_axi_gmem,0.180,31.579,0.000,0.000
-

reference-files/run/xrt.ini

+[Debug]
+profile=true
+timeline_trace=true
+data_transfer_trace=fine

rndgen.u250.ltx

+{
+    "ltx_root": {
+        "version": 4,
+        "minor": 0,
+        "ltx_data": [
+            {
+                "name": "EDA_PROBESET",
+                "active": true,
+                "debug_cores": [
+                    {
+                        "type": "XSDB_V3",
+                        "name": "pfm_top_i/static_region/slr1/user_debug_hub/inst/xsdbm",
+                        "spec": "labtools_xsdbm_v3",
+                        "clk_input_freq_hz": "50925925"
+                    },
+                    {
+                        "type": "XSDB_V3",
+                        "name": "pfm_top_i/static_region/slr1/mgmt_debug_hub/inst/xsdbm",
+                        "spec": "labtools_xsdbm_v3",
+                        "clk_input_freq_hz": "50925925"
+                    },
+                    {
+                        "type": "XSDB_V3",
+                        "name": "pfm_top_i/dynamic_region/debug_bridge_xsdbm/inst/xsdbm",
+                        "spec": "labtools_xsdbm_v3",
+                        "reconfigTop": "pfm_top_i/dynamic_region",
+                        "clk_input_freq_hz": "50925925"
+                    },
+                    {
+                        "type": "XSDBS_V2",
+                        "name": "pfm_top_i/static_region/slr1/pcie/inst/debug_wrapper_U/jtag_axi4l_m_inst",
+                        "spec": "labtools_xsdbslavelib_v2",
+                        "ipName": "jtag_axi",
+                        "uuid": "EB81CB65ED3C5402AD788BB6C3818280"
+                    },
+                    {
+                        "type": "XSDBS_V2",
+                        "name": "pfm_top_i/dynamic_region/memory_subsystem/inst/memory/ddr4_mem00",
+                        "spec": "labtools_xsdbslavelib_v2",
+                        "ipName": "DDR4_SDRAM",
+                        "reconfigTop": "pfm_top_i/dynamic_region",
+                        "uuid": "B26800E44324595D8ABC93BE6E65182E"
+                    }
+                ]
+            }
+        ]
+    }
+}
\ No newline at end of file

src_stream/cont.cpp

+#include "rndgen.hpp"
+
+#include <hls_stream.h>
+#include <ap_int.h>
+
+using namespace hls;
+using namespace std;
+
+
+void cont(const unsigned seed, const unsigned count, unsigned *out)
+{
+#pragma HLS INTERFACE m_axi port=out  offset=slave bundle=gmem
+#pragma HLS INTERFACE s_axilite port=seed bundle=control
+#pragma HLS INTERFACE s_axilite port=out  bundle=control
+#pragma HLS INTERFACE s_axilite port=return bundle=control
+
+
+#pragma HLS DATAFLOW
+    stream<unsigned> rndout;
+#pragma HLS STREAM variable = rndout depth = 16
+
+    rndgen(seed, count, rndout);
+
+    for (int i = 0; i < count; i++)
+        rndout >> out[i];
+}

src_stream/defines.hpp

+#pragma once
+
+#define REG_SIZE 32
+#define SET_SIZE 10000
+
+#define F1(x, y, z) ((x) ^ ((y) | (z)))
+#define F2(x, y, z) (!(x) ^ ((y) | (z)))
+
+#define F(x, y, z) F1((x), (y), (z))
+
+

src_stream/host.cpp

+#include "host.hpp"
+#include "defines.hpp"
+#include <iostream>
+#include <fstream>
+#include <chrono>
+
+using namespace std::chrono;
+
+int main(int argc, char** argv)
+{
+    uint32_t count;
+    if (argc == 2) {
+        count = SET_SIZE;
+    }
+    else if (argc == 3) {
+        count = atoi(argv[2]);
+    }
+    else {
+        std::cout << "Usage: " << argv[0] << " <XCLBIN File> *SET SIZE*" << std::endl;
+        return EXIT_FAILURE;
+    }
+
+    std::string binaryFile = argv[1];
+    size_t vector_size_bytes = sizeof(int) * count;
+    cl_int err;
+    unsigned fileBufSize;
+
+    // Allocate Memory in Host Memory
+    uint32_t seed = 2;
+    std::vector<uint32_t,aligned_allocator<uint32_t>> hw_results(SET_SIZE);
+    std::vector<uint32_t,aligned_allocator<uint32_t>> sw_results(SET_SIZE);
+
+
+    // Create the test data
+//    for(int i = 0 ; i < count ; i++)
+//    	hw_results[i] = 0;
+//    populate_results(sw_results, seed);
+
+// OPENCL HOST CODE AREA START
+
+    std::vector<cl::Device> devices = get_devices("Xilinx");
+    devices.resize(1);
+    cl::Device device = devices[0];
+
+    OCL_CHECK(err, cl::Context context(device, NULL, NULL, NULL, &err));
+    OCL_CHECK(err, cl::CommandQueue q(context, device, CL_QUEUE_PROFILING_ENABLE, &err));
+
+    char* fileBuf = read_binary_file(binaryFile, fileBufSize);
+    cl::Program::Binaries bins{{fileBuf, fileBufSize}};
+
+    OCL_CHECK(err, cl::Program program(context, devices, bins, NULL, &err));
+    OCL_CHECK(err, cl::Kernel krnl_rnd_gen(program,"cont", &err));
+
+    OCL_CHECK(err, cl::Buffer buffer_output(context,CL_MEM_USE_HOST_PTR | CL_MEM_WRITE_ONLY, vector_size_bytes, hw_results.data(), &err));
+
+    OCL_CHECK(err, err = krnl_rnd_gen.setArg(0, seed));
+    OCL_CHECK(err, err = krnl_rnd_gen.setArg(1, count));
+    OCL_CHECK(err, err = krnl_rnd_gen.setArg(2, buffer_output));
+
+    std::cout << "* * * RUN STARTED\n";
+    auto t1 = high_resolution_clock::now(); 
+    OCL_CHECK(err, err = q.enqueueTask(krnl_rnd_gen));
+    OCL_CHECK(err, err = q.enqueueMigrateMemObjects({buffer_output},CL_MIGRATE_MEM_OBJECT_HOST));
+    q.finish();
+    auto t2 = high_resolution_clock::now(); //clock_t c2 = clock();
+    std::cout << "* * * RUN DONE\n";
+
+// OPENCL HOST CODE AREA END
+
+    auto d1 = duration_cast<microseconds>(t2 - t1);
+    std::cout << "Task:   " << d1.count() << '\n';
+
+    // Compare the results of the Device to the simulation
+
+    bool match = true;
+/*      
+    std::ofstream fout("results/data.out");
+    for (int i = 0 ; i < count; i++){
+        fout << hw_results[i] << '\n';
+
+		if (sw_results[i] != hw_results[i]) {
+				match = false;
+				std::cout << "Not matched: " << sw_results[i] << ' ' << hw_results[i] << '\n';
+				break;
+		}
+    }
+
+    fout.close(); */
+    delete[] fileBuf;
+
+//    std::cout << "TEST " << (match ? "PASSED" : "FAILED") << std::endl;
+    return (match ? EXIT_SUCCESS : EXIT_FAILURE);
+}
+

src_stream/host.hpp

+#define CL_HPP_CL_1_2_DEFAULT_BUILD
+#define CL_HPP_TARGET_OPENCL_VERSION 120
+#define CL_HPP_MINIMUM_OPENCL_VERSION 120
+#define CL_HPP_ENABLE_PROGRAM_CONSTRUCTION_FROM_ARRAY_COMPATIBILITY 1
+#define CL_USE_DEPRECATED_OPENCL_1_2_APIS
+
+//OCL_CHECK doesn't work if call has templatized function call
+#define OCL_CHECK(error,call)                                       \
+    call;                                                           \
+    if (error != CL_SUCCESS) {                                      \
+      printf("%s:%d Error calling " #call ", error code is: %d\n",  \
+              __FILE__,__LINE__, error);                            \
+      exit(EXIT_FAILURE);                                           \
+    }
+    
+#define DATA_SIZE 100
+
+#include <vector>
+#include <unistd.h>
+#include <iostream>
+#include <fstream>
+#include <CL/cl2.hpp>
+#include "defines.hpp"
+
+template <typename T>
+struct aligned_allocator
+{
+  using value_type = T;
+  T* allocate(std::size_t num)
+  {
+    void* ptr = nullptr;
+    if (posix_memalign(&ptr,4096,num*sizeof(T)))
+      throw std::bad_alloc();
+    return reinterpret_cast<T*>(ptr);
+  }
+  void deallocate(T* p, std::size_t num)
+  {
+    free(p);
+  }
+};
+
+std::vector<cl::Device> get_devices(const std::string& vendor_name) {
+
+    size_t i;
+    cl_int err;
+    std::vector<cl::Platform> platforms;
+    OCL_CHECK(err, err = cl::Platform::get(&platforms));
+    cl::Platform platform;
+    for (i  = 0 ; i < platforms.size(); i++){
+        platform = platforms[i];
+        OCL_CHECK(err, std::string platformName = platform.getInfo<CL_PLATFORM_NAME>(&err));
+        if (platformName == vendor_name){
+            std::cout << "Found Platform" << std::endl;
+            std::cout << "Platform Name: " << platformName.c_str() << std::endl;
+            break;
+        }
+    }
+    if (i == platforms.size()) {
+        std::cout << "Error: Failed to find Xilinx platform" << std::endl;
+        exit(EXIT_FAILURE);
+    }
+   
+    //Getting ACCELERATOR Devices and selecting 1st such device 
+    std::vector<cl::Device> devices;
+    OCL_CHECK(err, err = platform.getDevices(CL_DEVICE_TYPE_ACCELERATOR, &devices));
+    return devices;
+}
+   
+char* read_binary_file(const std::string &xclbin_file_name, unsigned &nb) 
+{
+    std::cout << "INFO: Reading " << xclbin_file_name << std::endl;
+
+	if(access(xclbin_file_name.c_str(), R_OK) != 0) {
+		printf("ERROR: %s xclbin not available please build\n", xclbin_file_name.c_str());
+		exit(EXIT_FAILURE);
+	}
+    //Loading XCL Bin into char buffer 
+    std::cout << "Loading: '" << xclbin_file_name.c_str() << "'\n";
+    std::ifstream bin_file(xclbin_file_name.c_str(), std::ifstream::binary);
+    bin_file.seekg (0, bin_file.end);
+    nb = bin_file.tellg();
+    bin_file.seekg (0, bin_file.beg);
+    char *buf = new char [nb];
+    bin_file.read(buf, nb);
+    return buf;
+}
+
+void populate_results(std::vector<uint32_t,aligned_allocator<uint32_t>> &v, uint32_t seed) {
+    uint32_t X, Y;
+    X = seed;
+
+    for (uint32_t i = 0; i < SET_SIZE; i++) {
+        Y = 0;
+        for (uint32_t j = 0; j < REG_SIZE; j++) {
+            uint32_t b1 = (X & (1 << ((j + REG_SIZE-1) % REG_SIZE))) >> ((j + REG_SIZE-1) % REG_SIZE);
+            uint32_t b2 = (X & (1 << j)) >> j;
+            uint32_t b3 = (X & (1 << ((j + 1) % REG_SIZE))) >> ((j + 1) % REG_SIZE);
+            uint32_t r = F(b1, b2, b3) << j;
+            Y |= r;
+        }
+
+        v[i] = Y;
+        X = Y;
+    }
+}

src_stream/rndgen.hpp

+#include "defines.hpp"
+
+#include <hls_stream.h>
+#include <ap_int.h>
+using namespace hls;
+using namespace std;
+
+extern "C" {
+void rndgen(
+		const unsigned int seed,
+		const unsigned int count,
+		stream<unsigned> &out;
+	)
+{
+
+	ap_uint<REG_SIZE> X, Y;
+	X = seed;
+
+	generator: for (int i = 0; i < count; i++) {
+	#pragma HLS pipeline II=1
+
+		for (int j = 1; j < REG_SIZE - 1; j++) {
+		#pragma HLS unroll factor=30
+
+			Y[j] = F(X[j - 1], X[j], X[j+1]);
+		}
+
+		Y[0] = F(X[REG_SIZE - 1], X[0], X[1]);
+		Y[REG_SIZE - 1] = F(X[REG_SIZE - 2], X[REG_SIZE - 1], X[0]);
+
+		out << Y.to_uint();
+		X = Y;
+	}
+}
+}
+

timeline_kernels.csv

-Kernel trace events
-Device, Binary, Kernel, Compute Unit, Function, Data Type, Index, Start Time (ms), End Time (ms), Value

vitis_analyzer.jou

@@ -2,13 +2,12 @@
 # Vitis Analyzer v2020.1 (64-bit)
 # SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
 # 
-# Start of session at: Thu Jul 30 12:28:38 2020
-# Process ID: 12692
+# Start of session at: Wed Aug  5 14:58:38 2020
+# Process ID: 6425
 # Current directory: /home/atosa/Documents/RandomGen
-# Command line: vitis_analyzer ./profile_summary.csv
+# Command line: vitis_analyzer rndgen.u250.xclbin.link_summary
 # Log file: /home/atosa/Documents/RandomGen/vitis_analyzer.log
 # Journal file: /home/atosa/Documents/RandomGen/vitis_analyzer.jou
 #-----------------------------------------------------------
 start_gui
 create_project dummy
-close_project

vitis_pid11764.str

-/*
-
-Xilinx Vitis v2020.1.0 (64-bit) [Major: 2020, Minor: 1]
-SW Build 2902540 on Wed May 27 19:55:13 MDT 2020
-
-Process ID (PID): 11764
-License: Customer
-
-Current time: 	Thu Jul 30 12:24:05 CEST 2020
-Time zone: 	Central European Standard Time (Europe/Madrid)
-
-OS: Ubuntu
-OS Version: 4.15.0-111-generic
-OS Architecture: amd64
-Available processors (cores): 12
-
-Display: :9
-Screen size: 1920x1080
-Available screens: 1
-Available disk space: 219 GB
-
-Java version: 	9.0.4 64-bit
-Java home: 	/opt/Xilinx/Vitis/2020.1/tps/lnx64/jre9.0.4
-Java executable location: 	/opt/Xilinx/Vitis/2020.1/tps/lnx64/jre9.0.4/bin/java
-Java initial memory (-Xms): 	64 MB
-Java maximum memory (-Xmx):	 4 GB
-
-Java library paths: /opt/Xilinx/Vitis/2020.1/lib/lnx64.o/Ubuntu/18:/opt/Xilinx/Vitis/2020.1/lib/lnx64.o/Ubuntu:/opt/Xilinx/Vitis/2020.1/lib/lnx64.o:/opt/Xilinx/Vitis/2020.1/tps/lnx64/jre9.0.4/lib/:/opt/Xilinx/Vitis/2020.1/tps/lnx64/jre9.0.4/lib//server:/opt/Xilinx/Vitis/2020.1/lib/lnx64.o:/opt/Xilinx/Vitis/2020.1/lib/lnx64.o/Ubuntu/18:/opt/Xilinx/Vitis/2020.1/lib/lnx64.o/Ubuntu:/opt/Xilinx/Vitis/2020.1/lib/lnx64.o:/opt/xilinx/xrt/lib:/opt/xilinx/xrt/lib:/opt/xilinx/xrt/lib::/opt/Xilinx/Vitis/2020.1/bin/../lnx64/tools/dot/lib:/usr/java/packages/lib:/usr/lib64:/lib64:/lib:/usr/lib
-
-Java class paths: /opt/Xilinx/Vitis/2020.1/eclipse/lnx64.o//plugins/org.eclipse.equinox.launcher_1.5.0.v20180512-1130.jar
-LD_LIBRARY_PATH: /opt/Xilinx/Vitis
-
-User name: 	atosa
-User home directory: /home/atosa
-User working directory: /home/atosa/Documents/RandomGen
-User country: 	US
-User language: 	en
-User locale: 	en_US
-
-RDI_BASEROOT: /opt/Xilinx/Vitis
-HDI_APPROOT: /opt/Xilinx/Vitis/2020.1
-RDI_DATADIR: /opt/Xilinx/Vitis/2020.1/data
-RDI_BINDIR: /opt/Xilinx/Vitis/2020.1/bin
-
-Vitis preferences directory: /home/atosa/.Xilinx/Vitis/2020.1/
-Vitis workspace directory: /home/atosa/Documents
-Vitis workspace log file location: /home/atosa/Documents/.metadata/.log
-Engine tmp dir: 	
-
-Xilinx Environment Variables
-----------------------------
-XILINXD_LICENSE_FILE: 2100@flexlm.imdea
-XILINX_DSP: 
-XILINX_HLS: /opt/Xilinx/Vitis/2020.1
-XILINX_PLANAHEAD: /opt/Xilinx/Vitis/2020.1
-XILINX_SDK: /opt/Xilinx/Vitis/2020.1
-XILINX_VITIS: /opt/Xilinx/Vitis/2020.1
-XILINX_VIVADO: /opt/Xilinx/Vivado/2020.1
-XILINX_VIVADO_HLS: /opt/Xilinx/Vivado/2020.1
-XILINX_XRT: /opt/xilinx/xrt
-_RDI_DONT_SET_XILINX_AS_PATH: True
-
-
-Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-
-*/
-
-selectButton("Next", "Import Projects (Import Type)", "SdxArchiveImportWizard", "Button.NEXT");
-selectButton("Cancel", "Import Projects (Import Vitis Projects)", "SdxArchiveImportWizard", "Button.CANCEL");
-selectMenuItem("File", "WorkbenchWindow", "MenuItem.FILE");
-selectMenuItem("Import", "WorkbenchWindow", "MenuItem.IMPORT");
-selectRadioButton("Vitis project exported zip file", "Import Projects (Import Type)", "SdxArchiveImportWizard", "Button.VITIS_PROJECT_EXPORTED");
-selectRadioButton("Eclipse workspace or zip file", "Import Projects (Import Type)", "SdxArchiveImportWizard", "Button.ECLIPSE_WORKSPACE");
-selectButton("Next", "Import Projects (Import Type)", "SdxArchiveImportWizard", "Button.NEXT");
-selectButton("Browse", "Import Projects (Import Projects)", "SdxArchiveImportWizard", "Button.BROWSE");
-selectButton("Cancel", "Import Projects (Import Projects)", "SdxArchiveImportWizard", "Button.CANCEL");
-selectButton("Exit", "Confirm Exit", "MessageDialogWithToggle", "Button.EXIT");
-// Exiting Xilinx Vitis with a status code '0' at 7/30/20, 12:26:41 PM CEST
-// Elapsed time: 00:02:35
-

xilinx_u250_xdma_201830_2-0-rndgen.hw_emu.wcfg

-<?xml version="1.0" encoding="UTF-8"?>
-<wave_config>
-   <wave_state>
-   </wave_state>
-   <wvobject type="group" fp_name="HLS_Process_Summary_group">
-      <obj_property name="label">HLS Process Summary</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
-   </wvobject>
-   <wvobject type="group" fp_name="device_group">
-      <obj_property name="label">Device &quot;xilinx_u250_xdma_201830_2-0&quot;</obj_property>
-      <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
-      <wvobject type="group" fp_name="bin_group">
-         <obj_property name="label">Binary Container &quot;rndgen.hw_emu&quot;</obj_property>
-         <obj_property name="DisplayName">label</obj_property>
-         <obj_property name="isExpanded"></obj_property>
-         <wvobject type="group" fp_name="kernel_group">
-            <obj_property name="label">Kernel &quot;rndgen&quot; 1:1:1</obj_property>
-            <obj_property name="DisplayName">label</obj_property>
-            <obj_property name="isExpanded"></obj_property>
-            <wvobject type="group" fp_name="cu_group">
-               <obj_property name="label">Compute Unit: rndgen_1</obj_property>
-               <obj_property name="DisplayName">label</obj_property>
-               <obj_property name="isExpanded"></obj_property>
-               <obj_property name="Description_Data">Activity for compute unit rndgen_1</obj_property>
-               <obj_property name="EnumTransactionColorTable">1=blank</obj_property>
-               <obj_property name="EnumTransactionValueTable">1=blank;0=Running</obj_property>
-               <obj_property name="CustomSignalColor">#4DB34D</obj_property>
-               <obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
-               <obj_property name="UseCustomSignalColor">true</obj_property>
-               <obj_property name="Render_Data">/emu_wrapper/emu_i/rndgen_1/inst/ap_idle</obj_property>
-               <wvobject type="vbus" fp_name="stall_vbus">
-                  <obj_property name="label">CU Stalls (%)</obj_property>
-                  <obj_property name="DisplayName">label</obj_property>
-                  <obj_property name="Description_Data">CU Functions that are stalling (%)</obj_property>
-                  <obj_property name="Radix">BITCOUNTRADIX</obj_property>
-                  <obj_property name="SHOWPERCENTCOUNT">true</obj_property>
-                  <obj_property name="ShowWaveText">true</obj_property>
-                  <obj_property name="EnumTransactionColorTable">3=blank</obj_property>
-                  <obj_property name="EnumTransactionValueTable">3=blank</obj_property>
-                  <obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
-                  <obj_property name="CustomSignalColor">#FF7F27</obj_property>
-                  <obj_property name="UseCustomSignalColor">true</obj_property>
-                  <wvobject db_ref_id="1" type="logic" fp_name="/emu_wrapper/emu_i/rndgen_1/inst//ap_ext_blocking_n">
-                     <obj_property name="label">Top level: External Memory</obj_property>
-                     <obj_property name="Description_Data">Stalls from accessing external memory</obj_property>
-                     <obj_property name="DisplayName">label</obj_property>
-                     <obj_property name="EnumTransactionColorTable">1=blank</obj_property>
-                     <obj_property name="EnumTransactionValueTable">1=blank;0=stall</obj_property>
-                     <obj_property name="ShowWaveText">false</obj_property>
-                     <obj_property name="CustomSignalColor">#FF7F27</obj_property>
-                     <obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
-                     <obj_property name="UseCustomSignalColor">true</obj_property>
-                  </wvobject>
-                  <wvobject db_ref_id="1" type="logic" fp_name="/emu_wrapper/emu_i/rndgen_1/inst//ap_str_blocking_n">
-                     <obj_property name="label">Top level: External Stream</obj_property>
-                     <obj_property name="Description_Data">Stalls from accessing pipes between compute units</obj_property>
-                     <obj_property name="DisplayName">label</obj_property>
-                     <obj_property name="EnumTransactionColorTable">1=blank</obj_property>
-                     <obj_property name="EnumTransactionValueTable">1=blank;0=stall</obj_property>
-                     <obj_property name="ShowWaveText">false</obj_property>
-                     <obj_property name="CustomSignalColor">#FF7F27</obj_property>
-                     <obj_property name="WaveformStyle">STYLE_ENUM_TRANSACTION</obj_property>
-                     <obj_property name="UseCustomSignalColor">true</obj_property>
-                  </wvobject>
-               </wvobject>
-               <wvobject type="group" fp_name="trans_group">
-                  <obj_property name="label">Data Transfers</obj_property>
-                  <obj_property name="DisplayName">label</obj_property>
-                  <obj_property name="isExpanded"></obj_property>
-                  <wvobject type="protoinst" fp_name="/emu_wrapper/emu_i/rndgen_1/m_axi_gmem">
-                  </wvobject>
-               </wvobject>
-            </wvobject>
-         </wvobject>
-      </wvobject>
-   </wvobject>
-</wave_config>