Commit 1ee0488d authored by Zsolt Istvan's avatar Zsolt Istvan
Browse files

issues fixed around the regex module 949a6f2e6a5f

parent 07e3a412
......@@ -15,6 +15,7 @@
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module nukv_fifogen #(
parameter ADDR_BITS=5, // number of bits of address bus
parameter DATA_SIZE=16 // number of bits of data bus
......@@ -74,7 +75,7 @@ generate
FIFO36E1 #(
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(ADDR_BITS>8 ? 2**ADDR_BITS-8 : 2**ADDR_BITS), // Sets almost full threshold
.ALMOST_FULL_OFFSET(2**ADDR_BITS-8), // Sets almost full threshold
.DATA_WIDTH(72), // Sets data width to 4-72
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
.EN_ECC_READ("FALSE"), // Enable ECC decoder, FALSE, TRUE
......@@ -210,7 +211,7 @@ generate
FIFO36E1 #(
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(2**ADDR_BITS), // Sets almost full threshold
.ALMOST_FULL_OFFSET(2**ADDR_BITS-8), // Sets almost full threshold
.DATA_WIDTH(18), // Sets data width to 4-18
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
.EN_ECC_READ("FALSE"), // Enable ECC decoder, FALSE, TRUE
......
......@@ -406,9 +406,13 @@ always @(posedge clk) begin
rst_regd <= rst;
end
reg rst_faster0;
always @(posedge clk_faster) begin
frst <= rst_regd;
rst_faster <= frst | ~fclk_locked;
rst_faster0 <= frst | ~fclk_locked;
rst_faster <= rst_faster0;
end
......@@ -1139,7 +1143,7 @@ nukv_fifogen #(
wire predconf_regex_ready;
wire predconf_pred0_ready;
wire predconf_predother_ready;
assign predconf_b_ready = predconf_regex_ready & predconf_predother_ready & predconf_pred0_ready;
assign predconf_b_ready = predconf_regex_ready & predconf_predother_ready;
nukv_fifogen #(
.DATA_SIZE(512+96+1),
......@@ -1149,7 +1153,7 @@ nukv_fifogen #(
.rst(rst),
.s_axis_tdata({predconf_data, predconf_scan}),
.s_axis_tvalid(predconf_valid & predconf_ready),
.s_axis_tvalid(predconf_valid),
.s_axis_tready(predconf_ready),
.m_axis_tdata(predconf_b_fulldata),
......@@ -1168,7 +1172,7 @@ assign value_read_data = value_read_data_buf;
assign value_read_last = 0;
wire [512:0] regexin_data;
wire [513:0] regexin_data;
wire regexin_valid;
wire regexin_ready;
wire regexin_prebuf_ready;
......@@ -1181,13 +1185,17 @@ wire regexout_data;
wire regexout_valid;
wire regexout_ready;
wire buffer_violation;
wire before_get_ready;
wire before_get_almfull;
wire condin_ready;
wire cond_valid;
wire cond_ready;
wire cond_drop;
assign buffer_violation = ~cond_ready & before_get_ready;
nukv_Predicate_Eval_Pipeline_v2
......@@ -1198,7 +1206,7 @@ nukv_Predicate_Eval_Pipeline_v2
.clk(clk),
.rst(rst),
.pred_data({predconf_data[META_WIDTH+MEMORY_WIDTH-1 : META_WIDTH], predconf_data[META_WIDTH-1:0]}),
.pred_data({predconf_b_data[META_WIDTH+MEMORY_WIDTH-1 : META_WIDTH], predconf_b_data[META_WIDTH-1:0]}),
.pred_valid(predconf_b_valid & predconf_b_ready),
.pred_ready(predconf_predother_ready),
.pred_scan((SUPPORT_SCANS==1) ? predconf_b_scan : 0),
......@@ -1210,7 +1218,7 @@ nukv_Predicate_Eval_Pipeline_v2
.value_ready(value_read_ready),
.output_valid(value_frompred_valid),
.output_ready(value_frompred_ready & regexin_prebuf_ready),
.output_ready(value_frompred_ready),
.output_data(value_frompred_data),
.output_last(value_frompred_last),
.output_drop(value_frompred_drop),
......@@ -1226,30 +1234,31 @@ nukv_Predicate_Eval_Pipeline_v2
);
assign predconf_pred0_ready = 1;
// REGEX ---------------------------------------------------
wire toregex_ready;
assign value_frompred_ready = toregex_ready & condin_ready & before_get_ready;
fifo_generator_512_shallow_sync
//#(
// .DATA_SIZE(512+1),
// .ADDR_BITS(7)
//)
fifo_sidewait_regex (
fifo_toward_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(value_frompred_data),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready & regexin_prebuf_ready),
.s_axis_tready(regexin_prebuf_ready),
.s_axis_tuser(0),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready),
.s_axis_tready(toregex_ready),
.s_axis_tuser(value_frompred_drop),
.s_axis_tlast(value_frompred_last),
.m_axis_tdata(regexin_data[511:0]),
.m_axis_tvalid(regexin_valid),
.m_axis_tready(regexin_ready),
.m_axis_tuser(),
.m_axis_tuser(regexin_data[513]),
.m_axis_tlast(regexin_data[512])
);
......@@ -1258,9 +1267,6 @@ assign regexconf_data[511] = scan_mode_on;
assign regexconf_valid = predconf_b_valid & predconf_b_ready;
assign predconf_regex_ready = regexconf_ready;
assign regexout_ready = cond_ready;
wire [511:0] regexconf_buf_data;
wire regexconf_buf_valid;
wire regexconf_buf_ready;
......@@ -1330,8 +1336,6 @@ fifo_generator_1byte_sync
);
assign before_get_ready = condin_ready & value_frompred_ready;
nukv_fifogen #(
.DATA_SIZE(MEMORY_WIDTH),
.ADDR_BITS(8)
......@@ -1340,9 +1344,9 @@ nukv_fifogen #(
.rst(rst),
.s_axis_tdata(value_frompred_data),
.s_axis_tvalid(value_frompred_valid & before_get_ready & regexin_prebuf_ready),
.s_axis_tready(value_frompred_ready),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready),
.s_axis_tready(before_get_ready),
.m_axis_tdata(value_frompred_b_data),
.m_axis_tvalid(value_frompred_b_valid),
.m_axis_tready(value_frompred_b_ready)
......@@ -1358,7 +1362,7 @@ nukv_fifogen #(
.rst(rst),
.s_axis_tdata(value_frompred_drop),
.s_axis_tvalid(value_frompred_last & value_frompred_valid & before_get_ready),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready & value_frompred_last ),
.s_axis_tready(condin_ready),
.m_axis_tdata(cond_drop),
......@@ -1378,6 +1382,8 @@ wire read_decision;
assign decision_is_valid = cond_valid & regexout_valid;
assign decision_is_drop = cond_drop | ~regexout_data;
assign cond_ready = read_decision & decision_is_valid;
assign regexout_ready = read_decision & decision_is_valid;
nukv_Value_Get #(.SUPPORT_SCANS(SUPPORT_SCANS))
valuegetter
......@@ -1425,7 +1431,7 @@ reg[191:0] data_aux;
// -------------------------------------------------
/*
/* */
wire [35:0] control0, control1;
......@@ -1452,7 +1458,7 @@ reg[191:0] data_aux;
old_scan_mode <= scan_mode_on;
data_aux <= {value_read_data[0 +: 96], upd_rdcmd_data [32+:6],upd_rdcmd_data[0+:26]};
//data_aux <= {value_read_data[0 +: 96], upd_rdcmd_data [32+:6],upd_rdcmd_data[0+:26]};
debug_r[0] <= s_axis_tvalid ;
......@@ -1524,9 +1530,11 @@ reg[191:0] data_aux;
//debug_r[58] <= malloc_valid;
//debug_r[64 +: 32] <= {malloc_error_state};
//debug_r[64 +: 6] <= {regexout_ready, regexout_valid, cond_ready, cond_valid, regexin_prebuf_ready, (value_frompred_valid & value_frompred_ready & regexin_prebuf_ready)};
//debug_r[128 +: 128] <= data_aux;
// 71 70 69 68 67 66 65 64
debug_r[64 +: 8] <= {value_frompred_b_ready,value_frompred_b_valid,regexout_ready, regexout_valid, cond_ready, cond_valid, regexin_ready, regexin_valid};
debug_r[128 +: 128] <= data_aux;
......
......@@ -69,9 +69,10 @@ reg [REGEX_COUNT_BITS-1:0] output_regex_engine;
reg config_wait;
reg regex_inputbuffer_ok;
reg regex_inputbuffer_pre;
reg [7:0] config_ahead;
assign input_ready = (regex_inputbuffer_ok);
assign config_ready = ~regex_input_enable[config_regex_engine] && (regex_inputbuffer_ok);
assign config_ready = ~regex_input_enable[config_regex_engine] && (regex_inputbuffer_ok) && (config_ahead<MAX_REGEX_ENGINES-1);
reg rstBuf;
......@@ -88,6 +89,7 @@ always @(posedge clk) begin
config_wait <= 0;
regex_inputbuffer_ok <= 0;
regex_inputbuffer_pre <= 0;
config_ahead <= 0;
end
else begin
regex_input_enable <= 0;
......@@ -100,6 +102,8 @@ always @(posedge clk) begin
regex_input_prebuf[config_regex_engine] <= config_data;
regex_input_enable[config_regex_engine] <= 1;
regex_input_type[config_regex_engine] <= 1;
config_ahead <= config_ahead+1;
if (config_regex_engine==MAX_REGEX_ENGINES-1) begin
config_regex_engine <= 0;
......@@ -118,6 +122,13 @@ always @(posedge clk) begin
end
if (input_ready==1 && input_valid==1) begin
if (config_ready==1 && config_valid==1 && input_last==1) begin
config_ahead <= config_ahead;
end else if (input_last==1) begin
config_ahead <= config_ahead-1;
end
regex_input_prebuf[current_regex_engine] <= input_data;
regex_input_enable[current_regex_engine] <= 1;
regex_input_type[current_regex_engine] <= 0;
......@@ -184,7 +195,7 @@ generate
rem_top_ff rem_top_instance (
.clk(fast_clk),
.rst(fast_rst),
.softRst(softReset[X]),
.softRst(0),//softReset[X]),
.input_valid(regex_input_hasdata[X]),
.input_data(regex_input_data[X][511:0]),
......
......@@ -58,6 +58,7 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
reg [STATE_COUNT*(CHAR_COUNT)-1:0] config_state_pred;
reg [STATE_COUNT*STATE_COUNT-1:0] config_state_act;
reg restart;
reg wait_new;
reg wait_conf;
......@@ -164,6 +165,7 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
wait_new <= 1;
wait_conf <= 1;
restart <= 0;
need_purge <= 0;
input_ready <= 1;
......@@ -184,8 +186,10 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
end
else begin
if (softRst) begin
if (softRst | restart) begin
wait_conf <= 1;
wait_new <= 1;
restart <= 0;
end
input_wasvalid <= input_valid;
......@@ -231,7 +235,7 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
input_ready <= 1;
end
if (wait_conf==0) begin
if (restart==0 && wait_conf==0) begin
if (!input_ready && input_hasdata==1 && wait_new==1) begin
byte_addr <= 2;
......@@ -279,7 +283,7 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
end
else begin
byte_addr <= 0;
wait_new <= 1;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
......@@ -299,7 +303,7 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
else begin
waiting_pred <= 0;
byte_addr <= 0;
wait_new <= 1;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
......@@ -308,7 +312,7 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
if (!input_hasdata && output_valid==1 && waiting_pred==1) begin
waiting_pred <= 0;
byte_addr <= 0;
wait_new <= 1;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
......@@ -320,7 +324,7 @@ module rem_top_ff #(parameter CHAR_COUNT=16, DELIMITER=0, STATE_COUNT=4)
waiting_pred <= 0;
byte_addr <= 0;
wait_new <= 1;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
......
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